<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27331">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Get rid of non-local header treated as local<br><br>Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/amd/car/post_cache_as_ram.c<br>M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>M src/cpu/intel/haswell/romstage.c<br>M src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl<br>M src/mainboard/asus/kcma-d8/dsdt.asl<br>M src/mainboard/asus/kfsn4-dre/dsdt.asl<br>M src/mainboard/asus/kgpe-d16/dsdt.asl<br>M src/mainboard/asus/p2b-ls/dsdt.asl<br>M src/mainboard/asus/p2b/dsdt.asl<br>M src/southbridge/intel/fsp_rangeley/romstage.c<br>M src/southbridge/intel/lynxpoint/early_pch.c<br>11 files changed, 26 insertions(+), 25 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/27331/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c</span><br><span>index 2fb46d2..32ea166 100644</span><br><span>--- a/src/cpu/amd/car/post_cache_as_ram.c</span><br><span>+++ b/src/cpu/amd/car/post_cache_as_ram.c</span><br><span>@@ -31,7 +31,7 @@</span><br><span> #include "cpu/amd/car/disable_cache_as_ram.c"</span><br><span> </span><br><span> // For set_sysinfo_in_ram()</span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge/amd/amdfam10/raminit.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/amd/amdfam10/raminit.h></span><br><span> </span><br><span> #if CONFIG_RAMTOP <= 0x100000</span><br><span> #error "You need to set CONFIG_RAMTOP greater than 1M"</span><br><span>diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c</span><br><span>index 562a267..4602de9 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> #include <cpu/x86/pae.h></span><br><span> #include <pc80/mc146818rtc.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge/amd/amdfam10/amdfam10.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/amd/amdfam10/amdfam10.h></span><br><span> #include <cpu/amd/model_10xxx_rev.h></span><br><span> #include <cpu/cpu.h></span><br><span> #include <cpu/x86/cache.h></span><br><span>@@ -97,6 +97,7 @@</span><br><span> enable_cache();</span><br><span> </span><br><span> /* Set up other MTRRs */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> amd_setup_mtrrs();</span><br><span> } else {</span><br><span> while (!fam15h_startup_flags[id.nodeid][id.coreid - 1]) {</span><br><span>diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c</span><br><span>index 0e91dae..a26b549 100644</span><br><span>--- a/src/cpu/intel/haswell/romstage.c</span><br><span>+++ b/src/cpu/intel/haswell/romstage.c</span><br><span>@@ -38,10 +38,10 @@</span><br><span> #include <ec/google/chromeec/ec.h></span><br><span> #endif</span><br><span> #include "haswell.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge/intel/haswell/haswell.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge/intel/haswell/raminit.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "southbridge/intel/lynxpoint/pch.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "southbridge/intel/lynxpoint/me.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/haswell/haswell.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/haswell/raminit.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/lynxpoint/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/lynxpoint/me.h></span><br><span> #include <security/tpm/tspi.h></span><br><span> #include <cpu/intel/romstage.h></span><br><span> </span><br><span>diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl</span><br><span>index 54ead92..f8709a4 100644</span><br><span>--- a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl</span><br><span>+++ b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl</span><br><span>@@ -230,5 +230,5 @@</span><br><span> Z00A, 8</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- #include "northbridge/amd/amdfam10/amdfam10_util.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/amd/amdfam10/amdfam10_util.asl></span><br><span> }</span><br><span>diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl</span><br><span>index 5754d7c..b6dd211 100644</span><br><span>--- a/src/mainboard/asus/kcma-d8/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/kcma-d8/dsdt.asl</span><br><span>@@ -39,8 +39,8 @@</span><br><span> 0x00000001 /* OEM Revision */</span><br><span> )</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- #include "northbridge/amd/amdfam10/amdfam10_util.asl"</span><br><span style="color: hsl(0, 100%, 40%);">- #include "southbridge/amd/sr5650/acpi/sr5650.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/amd/amdfam10/amdfam10_util.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/amd/sr5650/acpi/sr5650.asl></span><br><span> </span><br><span> /* Some global data */</span><br><span> Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */</span><br><span>@@ -427,7 +427,7 @@</span><br><span> {</span><br><span> Name (_ADR, 0x00110000) // _ADR: Address</span><br><span> Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4</span><br><span style="color: hsl(0, 100%, 40%);">- #include "southbridge/amd/sb700/acpi/sata.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/amd/sb700/acpi/sata.asl></span><br><span> }</span><br><span> </span><br><span> /* 0:12.0 SP5100 USB 0 */</span><br><span>@@ -477,7 +477,7 @@</span><br><span> {</span><br><span> Name (_ADR, 0x00140001) // _ADR: Address</span><br><span> Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4</span><br><span style="color: hsl(0, 100%, 40%);">- #include "southbridge/amd/sb700/acpi/ide.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/amd/sb700/acpi/ide.asl></span><br><span> }</span><br><span> </span><br><span> /* 0:14.3 SP5100 LPC */</span><br><span>diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl</span><br><span>index 575715c..f3d59ce 100644</span><br><span>--- a/src/mainboard/asus/kfsn4-dre/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl</span><br><span>@@ -39,7 +39,7 @@</span><br><span> 0x00000001 /* OEM Revision */</span><br><span> )</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- #include "northbridge/amd/amdfam10/amdfam10_util.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/amd/amdfam10/amdfam10_util.asl></span><br><span> </span><br><span> /* Some global data */</span><br><span> Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */</span><br><span>@@ -404,7 +404,7 @@</span><br><span> Return (Local3)</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include "southbridge/nvidia/ck804/acpi/ck804.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/nvidia/ck804/acpi/ck804.asl></span><br><span> </span><br><span> /* PCI Routing Table Access */</span><br><span> Method (_PRT, 0, NotSerialized) {</span><br><span>diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl</span><br><span>index ab6547c..7b78b5d 100644</span><br><span>--- a/src/mainboard/asus/kgpe-d16/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/kgpe-d16/dsdt.asl</span><br><span>@@ -39,8 +39,8 @@</span><br><span> 0x00000001 /* OEM Revision */</span><br><span> )</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- #include "northbridge/amd/amdfam10/amdfam10_util.asl"</span><br><span style="color: hsl(0, 100%, 40%);">- #include "southbridge/amd/sr5650/acpi/sr5650.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/amd/amdfam10/amdfam10_util.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/amd/sr5650/acpi/sr5650.asl></span><br><span> </span><br><span> /* Some global data */</span><br><span> Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */</span><br><span>@@ -427,7 +427,7 @@</span><br><span> {</span><br><span> Name (_ADR, 0x00110000) // _ADR: Address</span><br><span> Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4</span><br><span style="color: hsl(0, 100%, 40%);">- #include "southbridge/amd/sb700/acpi/sata.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/amd/sb700/acpi/sata.asl></span><br><span> }</span><br><span> </span><br><span> /* 0:12.0 SP5100 USB 0 */</span><br><span>@@ -477,7 +477,7 @@</span><br><span> {</span><br><span> Name (_ADR, 0x00140001) // _ADR: Address</span><br><span> Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4</span><br><span style="color: hsl(0, 100%, 40%);">- #include "southbridge/amd/sb700/acpi/ide.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/amd/sb700/acpi/ide.asl></span><br><span> }</span><br><span> </span><br><span> /* 0:14.3 SP5100 LPC */</span><br><span>diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl</span><br><span>index 304a0f4..73d9508 100644</span><br><span>--- a/src/mainboard/asus/p2b-ls/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/p2b-ls/dsdt.asl</span><br><span>@@ -116,7 +116,7 @@</span><br><span> Return (0x0B)</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- #include "southbridge/intel/i82371eb/acpi/intx.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82371eb/acpi/intx.asl></span><br><span> </span><br><span> PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1)</span><br><span> PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2)</span><br><span>@@ -174,7 +174,7 @@</span><br><span> Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },</span><br><span> </span><br><span> })</span><br><span style="color: hsl(0, 100%, 40%);">- #include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl></span><br><span> </span><br><span> /* Begin southbridge block */</span><br><span> Device (PX40)</span><br><span>@@ -230,7 +230,7 @@</span><br><span> Return (BUF1)</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- #include "southbridge/intel/i82371eb/acpi/i82371eb.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82371eb/acpi/i82371eb.asl></span><br><span> }</span><br><span> Device (PX43)</span><br><span> {</span><br><span>diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl</span><br><span>index 8ddbf28..93f6afe 100644</span><br><span>--- a/src/mainboard/asus/p2b/dsdt.asl</span><br><span>+++ b/src/mainboard/asus/p2b/dsdt.asl</span><br><span>@@ -112,7 +112,7 @@</span><br><span> Return (0x0B)</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- #include "southbridge/intel/i82371eb/acpi/intx.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82371eb/acpi/intx.asl></span><br><span> </span><br><span> PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1)</span><br><span> PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2)</span><br><span>@@ -160,7 +160,7 @@</span><br><span> Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },</span><br><span> </span><br><span> })</span><br><span style="color: hsl(0, 100%, 40%);">- #include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl></span><br><span> </span><br><span> /* Begin southbridge block */</span><br><span> Device (PX40)</span><br><span>@@ -216,7 +216,7 @@</span><br><span> Return (BUF1)</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- #include "southbridge/intel/i82371eb/acpi/i82371eb.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82371eb/acpi/i82371eb.asl></span><br><span> }</span><br><span> Device (PX43)</span><br><span> {</span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c</span><br><span>index 74df691..2f598d8 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/romstage.c</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/romstage.c</span><br><span>@@ -27,7 +27,7 @@</span><br><span> #include <console/console.h></span><br><span> #include <drivers/intel/fsp1_0/fsp_util.h></span><br><span> #include <program_loading.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge/intel/fsp_rangeley/northbridge.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/fsp_rangeley/northbridge.h></span><br><span> #include "southbridge/intel/fsp_rangeley/soc.h"</span><br><span> #include "southbridge/intel/fsp_rangeley/gpio.h"</span><br><span> #include "southbridge/intel/fsp_rangeley/romstage.h"</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c</span><br><span>index cb4bc7e..4c45613 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/early_pch.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/early_pch.c</span><br><span>@@ -27,7 +27,7 @@</span><br><span> #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)</span><br><span> #include "lp_gpio.h"</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">-#include "southbridge/intel/common/gpio.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span> #endif</span><br><span> </span><br><span> const struct rcba_config_instruction pch_early_config[] = {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27331">change 27331</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27331"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa </div>
<div style="display:none"> Gerrit-Change-Number: 27331 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>