<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27325">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/southbridge.c: Add USB to aoac_devs table<br><br>Table aoac_devs is used to define control and status registers for devices<br>that can do D3/D0 transition (AOAC), so that there's a single delay while<br>all devices are being enabled simultaneously. USB host are being enabled<br>later, so that's an added delay when they are enabled. Adding USB to the<br>table should reduce post time by some milliseconds.<br><br>BUG=b:111056662<br>TEST=Build and boot grunt.<br><br>Change-Id: I8dc22b3d1e1662b9ef278b18338d31fe9424f227<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/southbridge.c<br>1 file changed, 3 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/27325/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 18e6c6c..ff64d9c 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -47,7 +47,9 @@</span><br><span>  { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 },</span><br><span>        { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 },</span><br><span>        { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 },</span><br><span style="color: hsl(0, 100%, 40%);">-   { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 }</span><br><span style="color: hsl(120, 100%, 40%);">+  { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { FCH_AOAC_D3_CONTROL_USB2, FCH_AOAC_D3_STATE_USB2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { FCH_AOAC_D3_CONTROL_USB3, FCH_AOAC_D3_STATE_USB3 }</span><br><span> };</span><br><span> </span><br><span> static int is_sata_config(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27325">change 27325</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27325"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8dc22b3d1e1662b9ef278b18338d31fe9424f227 </div>
<div style="display:none"> Gerrit-Change-Number: 27325 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>