<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27303">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Add MMU operation support<br><br>Enable MMU in bootblock and provide mt8183_mmu_after_dram() for<br>romstage after dram calibration ready.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Kukui.<br><br>Change-Id: I4e35f8276ca23de7fd13da3515b9f48d944ead32<br>Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com><br>---<br>M src/soc/mediatek/mt8183/Makefile.inc<br>M src/soc/mediatek/mt8183/bootblock.c<br>M src/soc/mediatek/mt8183/include/soc/addressmap.h<br>A src/soc/mediatek/mt8183/include/soc/mcucfg.h<br>A src/soc/mediatek/mt8183/include/soc/mmu_operations.h<br>A src/soc/mediatek/mt8183/mmu_operations.c<br>6 files changed, 489 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/27303/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>index 74b0ae8..8a9d07e 100644</span><br><span>--- a/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>+++ b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>@@ -1,6 +1,7 @@</span><br><span> ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y)</span><br><span> </span><br><span> bootblock-y += bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += mmu_operations.c</span><br><span> bootblock-$(CONFIG_SPI_FLASH) += spi.c</span><br><span> bootblock-y += ../common/timer.c</span><br><span> ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)</span><br><span>@@ -13,6 +14,8 @@</span><br><span> verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c</span><br><span> verstage-y += ../common/wdt.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += emi.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += mmu_operations.c</span><br><span> romstage-$(CONFIG_SPI_FLASH) += spi.c</span><br><span> romstage-y += ../common/timer.c</span><br><span> romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c</span><br><span>diff --git a/src/soc/mediatek/mt8183/bootblock.c b/src/soc/mediatek/mt8183/bootblock.c</span><br><span>index 4eca0f1..f92999b 100644</span><br><span>--- a/src/soc/mediatek/mt8183/bootblock.c</span><br><span>+++ b/src/soc/mediatek/mt8183/bootblock.c</span><br><span>@@ -14,9 +14,11 @@</span><br><span> */</span><br><span> </span><br><span> #include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/mmu_operations.h></span><br><span> #include <soc/wdt.h></span><br><span> </span><br><span> void bootblock_soc_init(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ mt8183_mmu_init();</span><br><span> mtk_wdt_init();</span><br><span> }</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>index a0d7f1c..a5c6f21 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #define __SOC_MEDIATEK_MT8183_INCLUDE_SOC_ADDRESSMAP_H__</span><br><span> </span><br><span> enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ MCUCFG_BASE = 0x0C530000,</span><br><span> IO_PHYS = 0x10000000,</span><br><span> DDR_BASE = 0x40000000</span><br><span> };</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/mcucfg.h b/src/soc/mediatek/mt8183/include/soc/mcucfg.h</span><br><span>new file mode 100644</span><br><span>index 0000000..0a1232a</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/mcucfg.h</span><br><span>@@ -0,0 +1,386 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_MEDIATEK_MT8183_MCUCFG_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_MEDIATEK_MT8183_MCUCFG_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mt8183_mcucfg_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_cache_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_mem_delsel0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_mem_delsel1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved1[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cache_mem_delsel0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cache_mem_delsel1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_axi_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved2[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_cfg_dis;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_clken_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_rst_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_misc_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_dbg_pwr_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_rw_rsvd0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_rw_rsvd1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ro_rsvd;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved3[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_l2_cache_parity1_rdata;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_l2_cache_parity2_rdata;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved4[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_rgu_dcm_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca53_specific_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_esr_case;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_esr_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_esr_trig_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved5[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ses_cg_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved6[216];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_dbg_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved7[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_ir_mon;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved8[32];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_dfd_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_cnt_l;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_cnt_h;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 misccfg_ro_rsvd;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved9[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_dbg_monitor_gpu;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_dbg_monitor_psys;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_dbg_monitor_mp1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_dbg_monitor_mp0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_dbg_monitor_mp2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved10[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_op_arid_mp0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_op_arid_mp1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_op_arid_mp2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved11[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s6_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved12[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_rst_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_dbg_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_dbg_flag;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_ca7l_ir_mon;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved13[32];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_dbg_mon_sel_a;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_dbg_mon;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 misccfg_sec_vio_status0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 misccfg_sec_vio_status1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_top_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_m0_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_m1_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_m2_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s1_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s2_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s3_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s4_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_m0_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_m1_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_m2_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s1_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s2_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s3_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s4_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_tra_dbg_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s5_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s5_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gic500_int_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 core_rst_en_latch;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved14[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dbg_core_ret;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_config_a;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_config1_a;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_gic_peribase_a;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_pinmux;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_range0_start;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_range0_end;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_range_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 l2c_mm_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved15[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 aclken_div;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pclken_div;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 l2c_sram_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 armpll_jit_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_addrmap;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_periphbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_nevntcntovfl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_acel_s1_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_bus_fabric_dcm_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcu_misc_dcm_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 xgpt_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 xgpt_idx;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved16[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_rw_rsvd0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_rw_rsvd1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved17[13];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gic500_delsel_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 etb_delsel_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 etb_rst_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved18[13];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_secur_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved19[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_cci_adb400_dcm_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_sync_dcm_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved20[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_sync_dcm_cluster_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sw_udi;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved21[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gic_sync_dcm;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 big_dbg_pwr_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gic_cpu_periphbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 axi_cpu_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved22[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsib_sys_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsib_sys_ctrl2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsib_sys_ctrl3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsib_sys_ctrl4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsib_dbg_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pwrmcu_apb2to1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved23[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_spmc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved24[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_spmc_sram_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved25[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_sw_rst_wait_cycle;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_pll_divider_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved26[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp2_pll_divider_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved27[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 bus_pll_divider_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved28[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clusterid_aff1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clusterid_aff2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 hack_ice_rom_table_access;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_top_mem_delay_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 l2c_cfg_mp0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved29[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 l2c_cfg_mp2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved30[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_cnt0to1_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_cnt2to3_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_cnt4to5_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_cnt6to7_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_cnt0to3_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_cnt4to7_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_ref_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved31[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_id_ext_cnt0to3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_id_ext_cnt4to7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_mask_ext_cnt0to3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_mask_ext_cnt4to7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved32[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 etb_acc_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 etb_ck_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved33[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_mp1_ocp_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved34[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_gic_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_gic_result;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_mcsib_sf1_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_mcsib_sf1_result;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_mcsib_sf2_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_mcsib_sf2_result;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved35[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_rstb;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_all_result;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved36[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_hang_monitor_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_hang_monitor_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved37[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_hang_monitor_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_hang_monitor_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved38[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp2_hang_monitor_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp2_hang_monitor_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved39[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gpu_hang_monitor_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gpu_hang_monitor_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved40[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 psys_hang_monitor_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 psys_hang_monitor_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved41[42];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en10;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en11;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en12;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en13;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en14;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en15;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en16;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en17;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en18;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en19;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved42[12];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl10;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl11;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl12;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl13;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl14;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl15;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl16;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl17;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl18;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl19;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved43[12];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_pwr_on;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_chain_legth_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_shift_clk_ratio;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_counter_return;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_sram_access;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_chain_length_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_chain_length_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_chain_length_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_test_so_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_test_so_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_num_of_test_so_gp;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_test_so_over_64;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_mask_out;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_sw_ns_trigger;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_mcsib;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_mcsib_sel_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_sram_base_addr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_sram_delsel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsib_iccs_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved44[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcu_all_pwr_on_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emi_wfifo;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsia_dcm_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved45[294];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcu_apb_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved46[384];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu_avg_stall_ratio;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_avg_stall_ratio_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu1_avg_stall_ratio_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu2_avg_stall_ratio_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu3_avg_stall_ratio_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_avg_stall_ratio_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_stall_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu1_stall_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu2_stall_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu3_stall_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_non_wfi_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu1_non_wfi_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu2_non_wfi_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu3_non_wfi_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved47[370];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_sparkvretcntrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_sparken;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_amuxsel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cg_dis;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu0_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu1_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu2_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu3_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_spark_debug_overwrite;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved48[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu0_spmc_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu1_spmc_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu2_spmc_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu3_spmc_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sesv3_rg_toggle;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved49[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_sync_dcm_cgavg_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_sync_dcm_cgavg_fact;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_sync_dcm_cgavg_rfact;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_sync_dcm_cgavg;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp0_cache_mem_delsel0, 0x0024);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp_dbg_ctrl, 0x0404);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp_dfd_ctrl, 0x0490);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, dvm_op_arid_mp0, 0x04c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, cci_s6_if_debug, 0x04e0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp1_rst_status, 0x0500);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mcusys_dbg_mon_sel_a, 0x0590);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, dbg_core_ret, 0x05fc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, aclken_div, 0x0640);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mcusys_rw_rsvd0, 0x0684);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, gic500_delsel_ctl, 0x06c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp_gen_timer_reset_mask_secur_en, 0x0700);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp_cci_adb400_dcm_config, 0x0740);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mcsib_sys_ctrl1, 0x0770);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, bus_pll_divider_cfg, 0x07c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, clusterid_aff1, 0x07e0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, cci_bw_pmu_id_ext_cnt0to3, 0x0860);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, etb_acc_ctl, 0x08b0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mbista_mp1_ocp_con, 0x08c8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mbista_rstb, 0x08f0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp0_hang_monitor_ctrl0, 0x0900);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp1_hang_monitor_ctrl0, 0x0910);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp2_hang_monitor_ctrl0, 0x0920);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, gpu_hang_monitor_ctrl0, 0x0940);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, psys_hang_monitor_ctrl0, 0x0950);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, sec_pol_ctl_en0, 0x0a00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, int_pol_ctl0, 0x0a80);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, dfd_internal_ctl, 0x0b00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mcu_apb_base, 0x0ffc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp0_cpu_avg_stall_ratio, 0x1600);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, cpusys0_sparkvretcntrl, 0x1c00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, cpusys0_cpu0_spmc_ctl, 0x1c30);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp0_sync_dcm_cgavg_ctrl, 0x1c60);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp0_sync_dcm_cgavg, 0x1c6c);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_MEDIATEK_MT8183_MCUCFG_H */</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/mmu_operations.h b/src/soc/mediatek/mt8183/include/soc/mmu_operations.h</span><br><span>new file mode 100644</span><br><span>index 0000000..a268089</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/mmu_operations.h</span><br><span>@@ -0,0 +1,35 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __SOC_MEDIATEK_MT8183_MMU_OPERATIONS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __SOC_MEDIATEK_MT8183_MMU_OPERATIONS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/mmu.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DEV_MEM = MA_DEV | MA_S | MA_RW,</span><br><span style="color: hsl(120, 100%, 40%);">+ CACHED_MEM = MA_MEM | MA_NS | MA_RW,</span><br><span style="color: hsl(120, 100%, 40%);">+ SECURE_MEM = MA_MEM | MA_S | MA_RW,</span><br><span style="color: hsl(120, 100%, 40%);">+ UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern unsigned char _sram_l2c[];</span><br><span style="color: hsl(120, 100%, 40%);">+extern unsigned char _esram_l2c[];</span><br><span style="color: hsl(120, 100%, 40%);">+#define _sram_l2c_size (_esram_l2c - _sram_l2c)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mt8183_mmu_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void mt8183_mmu_after_dram(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif //__SOC_MEDIATEK_MT8183_MMU_OPERATIONS_H__</span><br><span>diff --git a/src/soc/mediatek/mt8183/mmu_operations.c b/src/soc/mediatek/mt8183/mmu_operations.c</span><br><span>new file mode 100644</span><br><span>index 0000000..94e9f45</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/mmu_operations.c</span><br><span>@@ -0,0 +1,62 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/mmu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <symbols.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/emi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/mcucfg.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/mmu_operations.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mt8183_mmu_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set 0x0 to the end of 2GB dram address as device memory */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SRAM is cached */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_sram, _sram_size, CACHED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* L2C SRAM is cached */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_sram_l2c, _sram_l2c_size, CACHED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set ttb as secure */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_ttb, _ttb_size, SECURE_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_enable();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mt8183_mmu_after_dram(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Map DRAM as cached now that it's up and running */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Unmap L2C SRAM so it can be reclaimed by L2 cache */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO: Implement true unmapping, and also use it for the zero-page! */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Careful: changing cache geometry while it's active is a bad idea! */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_disable();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Turn off L2C SRAM and return it to L2 cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_mcucfg->l2c_cfg_mp0, 7 << 8);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_enable();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27303">change 27303</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27303"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4e35f8276ca23de7fd13da3515b9f48d944ead32 </div>
<div style="display:none"> Gerrit-Change-Number: 27303 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>