<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27305">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek: Share PLL code among similar SOCs<br><br>Refactor PLL code which will be reused among similar SOCs.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Elm<br><br>Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c<br>Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com><br>---<br>A src/soc/mediatek/common/include/soc/pll.h<br>A src/soc/mediatek/common/pll.c<br>M src/soc/mediatek/mt8173/Makefile.inc<br>M src/soc/mediatek/mt8173/dramc_pi_basic_api.c<br>R src/soc/mediatek/mt8173/include/soc/mt_pll.h<br>M src/soc/mediatek/mt8173/pll.c<br>6 files changed, 260 insertions(+), 183 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/27305/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/common/include/soc/pll.h b/src/soc/mediatek/common/include/soc/pll.h</span><br><span>new file mode 100644</span><br><span>index 0000000..d49c3bf</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/common/include/soc/pll.h</span><br><span>@@ -0,0 +1,73 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_MEDIATEK_COMMON_PLL_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_MEDIATEK_COMMON_PLL_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/mt_pll.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MTK_TOPCKGEN ((struct mtk_topckgen_regs *)CKSYS_BASE)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MTK_APMIXED ((struct mtk_apmixed_regs *)APMIXED_BASE)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_PWR_ON (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_EN (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_ISO (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_RSTB_SHIFT (24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define NO_RSTB_SHIFT (255)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_PCW_CHG (1 << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_POSTDIV_MASK 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mux {</span><br><span style="color: hsl(120, 100%, 40%);">+ void *reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *upd_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mux_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mux_width;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 upd_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct pll {</span><br><span style="color: hsl(120, 100%, 40%);">+ void *reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *pwr_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *div_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *pcw_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 *div_rate;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rstb_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pcwbits;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 div_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pcw_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, \</span><br><span style="color: hsl(120, 100%, 40%);">+ _pcw_reg, _pcw_shift, _div_rate) \</span><br><span style="color: hsl(120, 100%, 40%);">+ [_id] = { \</span><br><span style="color: hsl(120, 100%, 40%);">+ .reg = &MTK_APMIXED->_reg, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pwr_reg = &MTK_APMIXED->_pwr_reg, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .rstb_shift = _rstb, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pcwbits = _pcwbits, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .div_reg = &MTK_APMIXED->_div_reg, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .div_shift = _div_shift, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pcw_reg = &MTK_APMIXED->_pcw_reg, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pcw_shift = _pcw_shift, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .div_rate = _div_rate, \</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void pll_set_pcw_change(const struct pll *pll);</span><br><span style="color: hsl(120, 100%, 40%);">+void mux_set_sel(const struct mux *mux, u32 sel);</span><br><span style="color: hsl(120, 100%, 40%);">+int pll_set_rate(const struct pll *pll, u32 rate);</span><br><span style="color: hsl(120, 100%, 40%);">+void mt_pll_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_MEDIATEK_COMMON_PLL_H */</span><br><span>diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c</span><br><span>new file mode 100644</span><br><span>index 0000000..feaf0ea</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/common/pll.c</span><br><span>@@ -0,0 +1,89 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pll.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENMASK(h, l) (BIT(h + 1) - BIT(l))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mux_set_sel(const struct mux *mux, u32 sel)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask = GENMASK(mux->mux_width - 1, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 val = read32(mux->reg);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ val &= ~(mask << mux->mux_shift);</span><br><span style="color: hsl(120, 100%, 40%);">+ val |= (sel & mask) << mux->mux_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(mux->reg, val);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mux->upd_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(mux->upd_reg, 1 << mux->upd_shift);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pll_calc_values(const struct pll *pll, u32 *pcw, u32 *postdiv,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 freq)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 fin_hz = CLK26M_HZ;</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 *div_rate = pll->div_rate;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 val;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(freq <= div_rate[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(freq >= 1 * GHz / 16);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (val = 1; div_rate[val] != 0; val++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (freq > div_rate[val])</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ val--;</span><br><span style="color: hsl(120, 100%, 40%);">+ *postdiv = val;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* _pcw = freq * 2^postdiv / fin * 2^pcwbits_fractional */</span><br><span style="color: hsl(120, 100%, 40%);">+ val += pll->pcwbits - PCW_INTEGER_BITS;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ *pcw = ((u64)freq << val) / fin_hz;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pll_set_rate_regs(const struct pll *pll, u32 pcw, u32 postdiv)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 val;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set postdiv */</span><br><span style="color: hsl(120, 100%, 40%);">+ val = read32(pll->div_reg);</span><br><span style="color: hsl(120, 100%, 40%);">+ val &= ~(PLL_POSTDIV_MASK << pll->div_shift);</span><br><span style="color: hsl(120, 100%, 40%);">+ val |= postdiv << pll->div_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* postdiv and pcw need to set at the same time if on same register */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pll->div_reg != pll->pcw_reg) {</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pll->div_reg, val);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = read32(pll->pcw_reg);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set pcw */</span><br><span style="color: hsl(120, 100%, 40%);">+ val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);</span><br><span style="color: hsl(120, 100%, 40%);">+ val |= pcw << pll->pcw_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pll->pcw_reg, val);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set pcw change */</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_pcw_change(pll);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int pll_set_rate(const struct pll *pll, u32 rate)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcw, postdiv;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_calc_values(pll, &pcw, &postdiv, rate);</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate_regs(pll, pcw, postdiv);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>index 56c966a..78e1a72 100644</span><br><span>--- a/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>+++ b/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>@@ -18,7 +18,7 @@</span><br><span> bootblock-y += bootblock.c</span><br><span> bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c</span><br><span> bootblock-y += i2c.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += pll.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += ../common/pll.c pll.c</span><br><span> bootblock-y += spi.c</span><br><span> bootblock-y += ../common/timer.c</span><br><span> bootblock-y += timer.c</span><br><span>@@ -47,7 +47,7 @@</span><br><span> ################################################################################</span><br><span> </span><br><span> romstage-$(CONFIG_SPI_FLASH) += flash_controller.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += pll.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += ../common/pll.c pll.c</span><br><span> romstage-y += ../common/timer.c</span><br><span> romstage-y += timer.c</span><br><span> </span><br><span>@@ -75,7 +75,7 @@</span><br><span> ramstage-y += da9212.c</span><br><span> ramstage-y += gpio.c</span><br><span> ramstage-y += ../common/wdt.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += pll.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += ../common/pll.c pll.c</span><br><span> ramstage-y += rtc.c</span><br><span> </span><br><span> ramstage-y += usb.c</span><br><span>diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c</span><br><span>index cb6cc2c..21c8308 100644</span><br><span>--- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c</span><br><span>+++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c</span><br><span>@@ -738,7 +738,7 @@</span><br><span> u32 msk;</span><br><span> </span><br><span> msk = BIT(7) | BIT(11) | BIT(15);</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&mt8173_apmixed->ap_pll_con3, msk);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&MTK_APMIXED->ap_pll_con3, msk);</span><br><span> </span><br><span> msk = BIT(0) | BIT(4) | BIT(8);</span><br><span> clrbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], msk);</span><br><span>@@ -756,7 +756,7 @@</span><br><span> u32 val;</span><br><span> </span><br><span> val = BIT(7) | BIT(11) | BIT(15);</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&mt8173_apmixed->ap_pll_con3, val);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&MTK_APMIXED->ap_pll_con3, val);</span><br><span> </span><br><span> val = BIT(0) | BIT(4) | BIT(8);</span><br><span> setbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], val);</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/mt_pll.h</span><br><span>similarity index 90%</span><br><span>rename from src/soc/mediatek/mt8173/include/soc/pll.h</span><br><span>rename to src/soc/mediatek/mt8173/include/soc/mt_pll.h</span><br><span>index 9b3cca3..25dbe82 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/pll.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/mt_pll.h</span><br><span>@@ -17,9 +17,8 @@</span><br><span> #define SOC_MEDIATEK_MT8173_PLL_H</span><br><span> </span><br><span> #include <soc/emi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/addressmap.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-struct mt8173_topckgen_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+struct mtk_topckgen_regs {</span><br><span> u32 clk_mode;</span><br><span> u32 dcm_cfg;</span><br><span> u32 reserved1[6];</span><br><span>@@ -97,12 +96,12 @@</span><br><span> u32 mbist_cfg_3; /* 0x314 */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-check_member(mt8173_topckgen_regs, clk_cfg_0, 0x40);</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(mt8173_topckgen_regs, clk_cfg_8, 0x100);</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(mt8173_topckgen_regs, clk_scp_cfg_0, 0x200);</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(mt8173_topckgen_regs, mbist_cfg_3, 0x314);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_topckgen_regs, clk_cfg_0, 0x40);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_topckgen_regs, clk_cfg_8, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x200);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_topckgen_regs, mbist_cfg_3, 0x314);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-struct mt8173_apmixed_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+struct mtk_apmixed_regs {</span><br><span> u32 ap_pll_con0;</span><br><span> u32 reserved1[1];</span><br><span> u32 ap_pll_con2; /* 0x008 */</span><br><span>@@ -187,12 +186,19 @@</span><br><span> u32 msdcpll2_pwr_con0; /* 0x2fc */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-check_member(mt8173_apmixed_regs, ap_pll_con2, 0x8);</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(mt8173_apmixed_regs, armca15pll_con0, 0x200);</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(mt8173_apmixed_regs, msdcpll2_pwr_con0, 0x2fc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_apmixed_regs, ap_pll_con2, 0x8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_apmixed_regs, armca15pll_con0, 0x200);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_apmixed_regs, msdcpll2_pwr_con0, 0x2fc);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct mt8173_topckgen_regs *const mt8173_topckgen = (void *)CKSYS_BASE;</span><br><span style="color: hsl(0, 100%, 40%);">-static struct mt8173_apmixed_regs *const mt8173_apmixed = (void *)APMIXED_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL_PWR_ON_DELAY = 5,</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL_ISO_DELAY = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL_EN_DELAY = 40,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ PCW_INTEGER_BITS = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span> </span><br><span> /* PLL rate */</span><br><span> enum {</span><br><span>@@ -283,7 +289,6 @@</span><br><span> };</span><br><span> </span><br><span> void mt_pll_post_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void mt_pll_init(void);</span><br><span> void mt_pll_set_aud_div(u32 rate);</span><br><span> void mt_pll_enable_ssusb_clk(void);</span><br><span> void mt_pll_raise_ca53_freq(u32 freq);</span><br><span>diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c</span><br><span>index d95f769..da00648 100644</span><br><span>--- a/src/soc/mediatek/mt8173/pll.c</span><br><span>+++ b/src/soc/mediatek/mt8173/pll.c</span><br><span>@@ -15,7 +15,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <assert.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span> #include <delay.h></span><br><span> #include <stddef.h></span><br><span> </span><br><span>@@ -23,8 +22,6 @@</span><br><span> #include <soc/infracfg.h></span><br><span> #include <soc/pll.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> enum mux_id {</span><br><span> TOP_AXI_SEL,</span><br><span> TOP_MEM_SEL,</span><br><span>@@ -68,20 +65,13 @@</span><br><span> TOP_NR_MUX</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define TOPCKGEN_REG(x) (CKSYS_BASE + offsetof(struct mt8173_topckgen_regs, x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define APMIXED_REG(x) (APMIXED_BASE + offsetof(struct mt8173_apmixed_regs, x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct mux {</span><br><span style="color: hsl(0, 100%, 40%);">- void *reg;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 mux_shift;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 mux_width;</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define MUX(_id, _reg, _mux_shift, _mux_width) \</span><br><span> [_id] = { \</span><br><span style="color: hsl(0, 100%, 40%);">- .reg = (void *)TOPCKGEN_REG(_reg), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .reg = &MTK_TOPCKGEN->_reg, \</span><br><span> .mux_shift = _mux_shift, \</span><br><span> .mux_width = _mux_width, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .upd_reg = NULL, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .upd_shift = 0, \</span><br><span> }</span><br><span> </span><br><span> static const struct mux muxes[] = {</span><br><span>@@ -136,24 +126,6 @@</span><br><span> MUX(TOP_RTC_SEL, clk_cfg_13, 24, 2),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mux_set_sel(const struct mux *mux, u32 sel)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 mask = GENMASK(mux->mux_width - 1, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- u32 val = read32(mux->reg);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- val &= ~(mask << mux->mux_shift);</span><br><span style="color: hsl(0, 100%, 40%);">- val |= (sel & mask) << mux->mux_shift;</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mux->reg, val);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLL_PWR_ON (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLL_EN (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLL_ISO (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLL_RSTB (1 << 24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLL_PCW_CHG (1 << 31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLL_POSTDIV_MASK 0x7</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCW_INTEGER_BITS 7</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> enum pll_id {</span><br><span> APMIXED_ARMCA15PLL,</span><br><span> APMIXED_ARMCA7PLL,</span><br><span>@@ -199,117 +171,54 @@</span><br><span> 0,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-struct pll {</span><br><span style="color: hsl(0, 100%, 40%);">- void *reg;</span><br><span style="color: hsl(0, 100%, 40%);">- void *pwr_reg;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 rstb;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 pcwbits;</span><br><span style="color: hsl(0, 100%, 40%);">- void *div_reg;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 div_shift;</span><br><span style="color: hsl(0, 100%, 40%);">- void *pcw_reg;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 pcw_shift;</span><br><span style="color: hsl(0, 100%, 40%);">- const u32 *div_rate;</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, \</span><br><span style="color: hsl(0, 100%, 40%);">- _pcw_reg, _pcw_shift, _div_rate) \</span><br><span style="color: hsl(0, 100%, 40%);">- [_id] = { \</span><br><span style="color: hsl(0, 100%, 40%);">- .reg = (void *)APMIXED_REG(_reg), \</span><br><span style="color: hsl(0, 100%, 40%);">- .pwr_reg = (void *)APMIXED_REG(_pwr_reg), \</span><br><span style="color: hsl(0, 100%, 40%);">- .rstb = _rstb, \</span><br><span style="color: hsl(0, 100%, 40%);">- .pcwbits = _pcwbits, \</span><br><span style="color: hsl(0, 100%, 40%);">- .div_reg = (void *)APMIXED_REG(_div_reg), \</span><br><span style="color: hsl(0, 100%, 40%);">- .div_shift = _div_shift, \</span><br><span style="color: hsl(0, 100%, 40%);">- .pcw_reg = (void *)APMIXED_REG(_pcw_reg), \</span><br><span style="color: hsl(0, 100%, 40%);">- .pcw_shift = _pcw_shift, \</span><br><span style="color: hsl(0, 100%, 40%);">- .div_rate = _div_rate, \</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static const struct pll plls[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_ARMCA15PLL, armca15pll_con0, armca15pll_pwr_con0, 0, 21,</span><br><span style="color: hsl(0, 100%, 40%);">- armca15pll_con1, 24, armca15pll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_ARMCA7PLL, armca7pll_con0, armca7pll_pwr_con0, PLL_RSTB, 21,</span><br><span style="color: hsl(0, 100%, 40%);">- armca7pll_con1, 24, armca7pll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_pwr_con0, PLL_RSTB, 21,</span><br><span style="color: hsl(0, 100%, 40%);">- mainpll_con0, 4, mainpll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_UNIVPLL, univpll_con0, univpll_pwr_con0, PLL_RSTB, 7,</span><br><span style="color: hsl(0, 100%, 40%);">- univpll_con0, 4, univpll_con1, 14, univpll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_MMPLL, mmpll_con0, mmpll_pwr_con0, 0, 21,</span><br><span style="color: hsl(0, 100%, 40%);">- mmpll_con1, 24, mmpll_con1, 0, mmpll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_pwr_con0, 0, 21,</span><br><span style="color: hsl(0, 100%, 40%);">- msdcpll_con0, 4, msdcpll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_VENCPLL, vencpll_con0, vencpll_pwr_con0, 0, 21,</span><br><span style="color: hsl(0, 100%, 40%);">- vencpll_con0, 4, vencpll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_pwr_con0, 0, 21,</span><br><span style="color: hsl(0, 100%, 40%);">- tvdpll_con0, 4, tvdpll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_MPLL, mpll_con0, mpll_pwr_con0, 0, 21,</span><br><span style="color: hsl(0, 100%, 40%);">- mpll_con0, 4, mpll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_VCODECPLL, vcodecpll_con0, vcodecpll_pwr_con0, 0, 21,</span><br><span style="color: hsl(0, 100%, 40%);">- vcodecpll_con0, 4, vcodecpll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_APLL1, apll1_con0, apll1_pwr_con0, 0, 31,</span><br><span style="color: hsl(0, 100%, 40%);">- apll1_con0, 4, apll1_con1, 0, pll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0, 0, 31,</span><br><span style="color: hsl(0, 100%, 40%);">- apll2_con0, 4, apll2_con1, 0, pll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_LVDSPLL, lvdspll_con0, lvdspll_pwr_con0, 0, 21,</span><br><span style="color: hsl(0, 100%, 40%);">- lvdspll_con0, 4, lvdspll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(0, 100%, 40%);">- PLL(APMIXED_MSDCPLL2, msdcpll2_con0, msdcpll2_pwr_con0, 0, 21,</span><br><span style="color: hsl(0, 100%, 40%);">- msdcpll2_con0, 4, msdcpll2_con1, 0, pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_ARMCA15PLL, armca15pll_con0, armca15pll_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ NO_RSTB_SHIFT, 21, armca15pll_con1, 24, armca15pll_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_ARMCA7PLL, armca7pll_con0, armca7pll_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL_RSTB_SHIFT, 21, armca7pll_con1, 24, armca7pll_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL_RSTB_SHIFT, 21, mainpll_con0, 4, mainpll_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_UNIVPLL, univpll_con0, univpll_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL_RSTB_SHIFT, 7, univpll_con0, 4, univpll_con1, 14,</span><br><span style="color: hsl(120, 100%, 40%);">+ univpll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_MMPLL, mmpll_con0, mmpll_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ NO_RSTB_SHIFT, 21, mmpll_con1, 24, mmpll_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ mmpll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ NO_RSTB_SHIFT, 21, msdcpll_con0, 4, msdcpll_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_VENCPLL, vencpll_con0, vencpll_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ NO_RSTB_SHIFT, 21, vencpll_con0, 4, vencpll_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ NO_RSTB_SHIFT, 21, tvdpll_con0, 4, tvdpll_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_MPLL, mpll_con0, mpll_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ NO_RSTB_SHIFT, 21, mpll_con0, 4, mpll_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_VCODECPLL, vcodecpll_con0, vcodecpll_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ NO_RSTB_SHIFT, 21, vcodecpll_con0, 4, vcodecpll_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_APLL1, apll1_con0, apll1_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ NO_RSTB_SHIFT, 31, apll1_con0, 4, apll1_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ NO_RSTB_SHIFT, 31, apll2_con0, 4, apll2_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_LVDSPLL, lvdspll_con0, lvdspll_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ NO_RSTB_SHIFT, 21, lvdspll_con0, 4, lvdspll_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_MSDCPLL2, msdcpll2_con0, msdcpll2_pwr_con0,</span><br><span style="color: hsl(120, 100%, 40%);">+ NO_RSTB_SHIFT, 21, msdcpll2_con0, 4, msdcpll2_con1, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_div_rate),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pll_set_rate_regs(const struct pll *pll, u32 pcw, u32 postdiv)</span><br><span style="color: hsl(120, 100%, 40%);">+void pll_set_pcw_change(const struct pll *pll)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 val;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* set postdiv */</span><br><span style="color: hsl(0, 100%, 40%);">- val = read32(pll->div_reg);</span><br><span style="color: hsl(0, 100%, 40%);">- val &= ~(PLL_POSTDIV_MASK << pll->div_shift);</span><br><span style="color: hsl(0, 100%, 40%);">- val |= postdiv << pll->div_shift;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* postdiv and pcw need to set at the same time if on same register */</span><br><span style="color: hsl(0, 100%, 40%);">- if (pll->div_reg != pll->pcw_reg) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(pll->div_reg, val);</span><br><span style="color: hsl(0, 100%, 40%);">- val = read32(pll->pcw_reg);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* set pcw */</span><br><span style="color: hsl(0, 100%, 40%);">- val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);</span><br><span style="color: hsl(0, 100%, 40%);">- val |= pcw << pll->pcw_shift;</span><br><span style="color: hsl(0, 100%, 40%);">- val |= PLL_PCW_CHG;</span><br><span style="color: hsl(0, 100%, 40%);">- write32(pll->pcw_reg, val);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void pll_calc_values(const struct pll *pll, u32 *pcw, u32 *postdiv,</span><br><span style="color: hsl(0, 100%, 40%);">- u32 freq)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const u32 fin_hz = CLK26M_HZ;</span><br><span style="color: hsl(0, 100%, 40%);">- const u32 *div_rate = pll->div_rate;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 val;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- assert(freq <= div_rate[0]);</span><br><span style="color: hsl(0, 100%, 40%);">- assert(freq >= 1 * GHz / 16);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (val = 1; div_rate[val] != 0; val++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (freq > div_rate[val])</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- val--;</span><br><span style="color: hsl(0, 100%, 40%);">- *postdiv = val;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* _pcw = freq * 2^postdiv / fin * 2^pcwbits_fractional */</span><br><span style="color: hsl(0, 100%, 40%);">- val += pll->pcwbits - PCW_INTEGER_BITS;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- *pcw = ((u64)freq << val) / fin_hz;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int pll_set_rate(const struct pll *pll, u32 rate)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pcw = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 postdiv;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pll_calc_values(pll, &pcw, &postdiv, rate);</span><br><span style="color: hsl(0, 100%, 40%);">- pll_set_rate_regs(pll, pcw, postdiv);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(pll->pcw_reg, PLL_PCW_CHG);</span><br><span> }</span><br><span> </span><br><span> void mt_pll_init(void)</span><br><span>@@ -317,10 +226,10 @@</span><br><span> int i;</span><br><span> </span><br><span> /* reduce CLKSQ disable time */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_apmixed->clksq_stb_con0, (0x05 << 8) | (0x01 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&MTK_APMIXED->clksq_stb_con0, (0x05 << 8) | (0x01 << 0));</span><br><span> /* extend PWR/ISO control timing to 1us */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_apmixed->pll_iso_con0, (0x8 << 16) | (0x8 << 0));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_apmixed->ap_pll_con6, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&MTK_APMIXED->pll_iso_con0, (0x8 << 16) | (0x8 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&MTK_APMIXED->ap_pll_con6, 0x00000000);</span><br><span> </span><br><span> /*************</span><br><span> * xPLL PWR ON</span><br><span>@@ -328,7 +237,8 @@</span><br><span> for (i = 0; i < APMIXED_NR_PLL; i++)</span><br><span> setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* wait for xPLL_PWR_ON ready (min delay is 1us) */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(PLL_PWR_ON_DELAY);</span><br><span> </span><br><span> /******************</span><br><span> * xPLL ISO Disable</span><br><span>@@ -361,14 +271,14 @@</span><br><span> for (i = 0; i < APMIXED_NR_PLL; i++)</span><br><span> setbits_le32(plls[i].reg, PLL_EN);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- udelay(40); /* wait for PLL stable (min delay is 20us) */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(PLL_EN_DELAY); /* wait for PLL stable (min delay is 20us) */</span><br><span> </span><br><span> /***************</span><br><span> * xPLL DIV RSTB</span><br><span> ****************/</span><br><span> for (i = 0; i < APMIXED_NR_PLL; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (plls[i].rstb)</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(plls[i].reg, plls[i].rstb);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (plls[i].rstb_shift != NO_RSTB_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift);</span><br><span> }</span><br><span> </span><br><span> /**************</span><br><span>@@ -378,8 +288,8 @@</span><br><span> /* enable infrasys DCM */</span><br><span> setbits_le32(&mt8173_infracfg->top_dcmctl, 0x1);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_topckgen->clk_mode, 0x1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_topckgen->clk_mode, 0x0); /* enable TOPCKGEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&MTK_TOPCKGEN->clk_mode, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&MTK_TOPCKGEN->clk_mode, 0x0); /* enable TOPCKGEN */</span><br><span> </span><br><span> /************</span><br><span> * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!</span><br><span>@@ -436,10 +346,10 @@</span><br><span> mux_set_sel(&muxes[TOP_MSDC30_1_SEL], 2); /* 2: msdcpll_d4 */</span><br><span> </span><br><span> /* enable scpsys clock off control */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_topckgen->clk_scp_cfg_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&MTK_TOPCKGEN->clk_scp_cfg_0,</span><br><span> (1 << 10) | (1 << 9) | (1 << 5) | (1 << 4) | (1 << 2) |</span><br><span> (1 << 1) | (1 << 0));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_topckgen->clk_scp_cfg_1,</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&MTK_TOPCKGEN->clk_scp_cfg_1,</span><br><span> (1 << 4) | (1 << 2) | (1 << 0));</span><br><span> }</span><br><span> </span><br><span>@@ -447,16 +357,16 @@</span><br><span> void mt_pll_enable_ssusb_clk(void)</span><br><span> {</span><br><span> /* set RG_LTECLKSQ_EN */</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&MTK_APMIXED->ap_pll_con0, 0x1);</span><br><span> udelay(100); /* wait for PLL stable */</span><br><span> </span><br><span> /* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1 << 1);</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&mt8173_apmixed->ap_pll_con2, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&MTK_APMIXED->ap_pll_con0, 0x1 << 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&MTK_APMIXED->ap_pll_con2, 0x1);</span><br><span> udelay(100); /* wait for PLL stable */</span><br><span> </span><br><span> /* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&mt8173_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&MTK_APMIXED->ap_pll_con2, (0x1 << 2) | (0x1 << 1));</span><br><span> }</span><br><span> </span><br><span> </span><br><span>@@ -487,19 +397,19 @@</span><br><span> </span><br><span> if (apll1) {</span><br><span> /* mclk */</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&mt8173_topckgen->clk_auddiv_0, 1 << 5);</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&mt8173_topckgen->clk_auddiv_1, 0xff << 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&MTK_TOPCKGEN->clk_auddiv_0, 1 << 5);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&MTK_TOPCKGEN->clk_auddiv_1, 0xff << 8,</span><br><span> mclk_div << 8);</span><br><span> /* bclk */</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&mt8173_topckgen->clk_auddiv_0, 0xf << 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&MTK_TOPCKGEN->clk_auddiv_0, 0xf << 24,</span><br><span> 7 << 24);</span><br><span> } else {</span><br><span> /* mclk */</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&mt8173_topckgen->clk_auddiv_0, 1 << 5);</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&mt8173_topckgen->clk_auddiv_2, 0xff << 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&MTK_TOPCKGEN->clk_auddiv_0, 1 << 5);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&MTK_TOPCKGEN->clk_auddiv_2, 0xff << 8,</span><br><span> mclk_div << 8);</span><br><span> /* bclk */</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&mt8173_topckgen->clk_auddiv_0, 0xf << 28,</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&MTK_TOPCKGEN->clk_auddiv_0, 0xf << 28,</span><br><span> 7 << 28);</span><br><span> }</span><br><span> }</span><br><span>@@ -513,19 +423,19 @@</span><br><span> u32 mpll_sdm_pcw_20_0 = 0xF13B1;</span><br><span> </span><br><span> /* disable MPLL for adjusting memory clk frequency */</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&mt8173_apmixed->mpll_con0, BIT(0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&MTK_APMIXED->mpll_con0, BIT(0));</span><br><span> /* MPLL configuration: mode selection */</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&mt8173_apmixed->mpll_con0, BIT(16));</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&mt8173_apmixed->mpll_con0, 0x7 << 4);</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&mt8173_apmixed->pll_test_con0, 1 << 31);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&MTK_APMIXED->mpll_con0, BIT(16));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&MTK_APMIXED->mpll_con0, 0x7 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&MTK_APMIXED->pll_test_con0, 1 << 31);</span><br><span> /* set RG_MPLL_SDM_PCW for feedback divide ratio */</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&mt8173_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&MTK_APMIXED->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0);</span><br><span> }</span><br><span> </span><br><span> void mt_mem_pll_config_post(void)</span><br><span> {</span><br><span> /* power up sequence starts: enable MPLL */</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&mt8173_apmixed->mpll_con0, BIT(0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&MTK_APMIXED->mpll_con0, BIT(0));</span><br><span> }</span><br><span> </span><br><span> void mt_mem_pll_mux(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27305">change 27305</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27305"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c </div>
<div style="display:none"> Gerrit-Change-Number: 27305 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>