<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27307">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/i945: Add macro for device 0:01.0<br><br>Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/intel/i945/early_init.c<br>M src/northbridge/intel/i945/i945.h<br>2 files changed, 20 insertions(+), 16 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/27307/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c</span><br><span>index 7de2c73..c741e51 100644</span><br><span>--- a/src/northbridge/intel/i945/early_init.c</span><br><span>+++ b/src/northbridge/intel/i945/early_init.c</span><br><span>@@ -575,25 +575,25 @@</span><br><span> */</span><br><span> </span><br><span> /* First we reset the secondary bus */</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);</span><br><span> reg16 |= (1 << 6); /* SRESET */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);</span><br><span> /* Read back and clear reset bit. */</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);</span><br><span> reg16 &= ~(1 << 6); /* SRESET */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS);</span><br><span> printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);</span><br><span> if (!(reg16 & 0x48))</span><br><span> goto disable_pciexpress_x16_link;</span><br><span> reg16 |= (1 << 4) | (1 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCI_DEV(0, 0x01, 0), SLOTSTS, reg16);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x00);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x00);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x0a);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x0a);</span><br><span> </span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224);</span><br><span> reg32 &= ~(1 << 8);</span><br><span>@@ -639,12 +639,12 @@</span><br><span> reg32 |= 1;</span><br><span> pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);</span><br><span> </span><br><span> reg16 |= (1 << 6);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);</span><br><span> reg16 &= ~(1 << 6);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "PCIe link training ...");</span><br><span> timeout = 0x7ffff;</span><br><span>@@ -700,17 +700,17 @@</span><br><span> /* Enable GPEs */</span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xec);</span><br><span> reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32);</span><br><span> </span><br><span> /* Virtual Channel Configuration: Only VC0 on PCIe x16 */</span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x114);</span><br><span> reg32 &= 0xffffff01;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32);</span><br><span> </span><br><span> /* Extended VC count */</span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x104);</span><br><span> reg32 &= ~(7 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32);</span><br><span> </span><br><span> /* Active State Power Management ASPM */</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h</span><br><span>index cc5f087..b5e7440 100644</span><br><span>--- a/src/northbridge/intel/i945/i945.h</span><br><span>+++ b/src/northbridge/intel/i945/i945.h</span><br><span>@@ -84,6 +84,10 @@</span><br><span> /* Device 0:1.0 PCI configuration space (PCI Express) */</span><br><span> </span><br><span> #define BCTRL1 0x3e /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SBUSN1 0x19 /* 8bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUBUSN1 0x1a /* 8bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SLOTSTS 0xba /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define VC0RCTL 0x114 /* 32bit */</span><br><span> #define PEGSTS 0x214 /* 32bit */</span><br><span> </span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27307">change 27307</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5 </div>
<div style="display:none"> Gerrit-Change-Number: 27307 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>