<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27296">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/i945: Correct udelay for Netburst<br><br>NetBurst have FSB information at MSR_EBC_FREQUENCY_ID.<br><br>Change-Id: I588383dbdfd3d630c605c7d4d6014a3f82354e68<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/intel/i945/udelay.c<br>1 file changed, 12 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/27296/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c</span><br><span>index 8447453..b02f13b 100644</span><br><span>--- a/src/northbridge/intel/i945/udelay.c</span><br><span>+++ b/src/northbridge/intel/i945/udelay.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #include <cpu/x86/tsc.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <cpu/intel/speedstep.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span> </span><br><span> /**</span><br><span>  * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock</span><br><span>@@ -30,9 +31,18 @@</span><br><span>  msr_t msr;</span><br><span>   u32 fsb = 0, divisor;</span><br><span>        u32 d;                  /* ticks per us */</span><br><span style="color: hsl(120, 100%, 40%);">+    u8 fsbcfg;</span><br><span style="color: hsl(120, 100%, 40%);">+    const u32 eax = cpuid_eax(1);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-       msr = rdmsr(MSR_FSB_FREQ);</span><br><span style="color: hsl(0, 100%, 40%);">-      switch (msr.lo & 0x07) {</span><br><span style="color: hsl(120, 100%, 40%);">+  if (((eax >> 8) & 0xf) == 0xf) {</span><br><span style="color: hsl(120, 100%, 40%);">+            msr = rdmsr(MSR_EBC_FREQUENCY_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+            fsbcfg = (msr.lo >> 16) & 0x7;</span><br><span style="color: hsl(120, 100%, 40%);">+      } else {</span><br><span style="color: hsl(120, 100%, 40%);">+              msr = rdmsr(MSR_FSB_FREQ);</span><br><span style="color: hsl(120, 100%, 40%);">+            fsbcfg = msr.lo & 0x7;</span><br><span style="color: hsl(120, 100%, 40%);">+    }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   switch (fsbcfg) {</span><br><span>    case 5:</span><br><span>              fsb = 400;</span><br><span>           break;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27296">change 27296</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27296"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I588383dbdfd3d630c605c7d4d6014a3f82354e68 </div>
<div style="display:none"> Gerrit-Change-Number: 27296 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>