<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27270">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Generate ACPI RMRR table<br><br>An ACPI RMRR table is requried for IOMMU to work properly with an<br>iGPU (without using passthrough mode), so create one along with the<br>DRHD DMAR table if the iGPU is present and enabled.<br><br>Test: build/boot google/chell and purism/librem13v2 with kernel<br>parameter 'intel_iommu=on' but without 'iommu=pt;' observe integrated<br>graphics functional without corruption.<br><br>Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/soc/intel/skylake/acpi.c<br>M src/soc/intel/skylake/include/soc/systemagent.h<br>M src/soc/intel/skylake/systemagent.c<br>3 files changed, 72 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27270/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c</span><br><span>index 4ad4831..e0516ab 100644</span><br><span>--- a/src/soc/intel/skylake/acpi.c</span><br><span>+++ b/src/soc/intel/skylake/acpi.c</span><br><span>@@ -551,15 +551,34 @@</span><br><span> const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff;</span><br><span> const bool gfxvten = MCHBAR32(GFXVTBAR) & 1;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 tolud_addr = sa_get_tolud_addr();</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 igd_rmrr_base = tolud_addr -</span><br><span style="color: hsl(120, 100%, 40%);">+ (sa_get_igd_mem_sz() + sa_get_gtt_mem_sz());</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 igd_rmrr_limit = tolud_addr - 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */</span><br><span> if (igfx_dev && igfx_dev->enabled && gfxvten &&</span><br><span> gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) {</span><br><span style="color: hsl(0, 100%, 40%);">- const unsigned long tmp = current;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned long tmp = current;</span><br><span> </span><br><span> current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar);</span><br><span> current += acpi_create_dmar_ds_pci(current, 0, 2, 0);</span><br><span> </span><br><span> acpi_dmar_drhd_fixup(tmp, current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Add RMRR entry</span><br><span style="color: hsl(120, 100%, 40%);">+ * Address calculations taken from edk2 reference implementation</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (tolud_addr > 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_rmrr(current, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ igd_rmrr_base, igd_rmrr_limit);</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_ds_pci(current, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SA_DEV_SLOT_IGD, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_dmar_rmrr_fixup(tmp, current);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> </span><br><span> struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB);</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h</span><br><span>index 8e53f54..9724b03 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/systemagent.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/systemagent.h</span><br><span>@@ -25,6 +25,12 @@</span><br><span> /* Device 0:0.0 PCI configuration space */</span><br><span> </span><br><span> #define EPBAR 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GGC_REG 0x50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GGC_GMS_MASK 0xff00</span><br><span style="color: hsl(120, 100%, 40%);">+#define GGC_GMS_OFST 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define GGC_GGMS_MASK 0xc0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GGC_GGMS_OFST 0x06</span><br><span style="color: hsl(120, 100%, 40%);">+#define GGC_GGMS_8MB 0x03</span><br><span> #define DMIBAR 0x68</span><br><span> #define SMRAM 0x88 /* System Management RAM Control */</span><br><span> #define D_OPEN (1 << 6)</span><br><span>@@ -47,6 +53,9 @@</span><br><span> #define MCH_DDR_POWER_LIMIT_HI 0x58e4</span><br><span> </span><br><span> bool soc_is_vtd_capable(void);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 sa_get_tolud_addr(void);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 sa_get_igd_mem_sz(void);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 sa_get_gtt_mem_sz(void);</span><br><span> </span><br><span> static const struct sa_mmio_descriptor soc_vtd_resources[] = {</span><br><span> { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },</span><br><span>diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c</span><br><span>index 2c4408fe..3911e80 100644</span><br><span>--- a/src/soc/intel/skylake/systemagent.c</span><br><span>+++ b/src/soc/intel/skylake/systemagent.c</span><br><span>@@ -36,6 +36,49 @@</span><br><span> !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+u32 sa_get_tolud_addr(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *const root_dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return root_dev ? pci_read_config32(root_dev, TOLUD) & ~(0x01) : 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u32 sa_get_igd_mem_sz(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *const root_dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 igd_mode;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 igd_mem_sz;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!root_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ igd_mode = (pci_read_config16(root_dev, GGC_REG) & GGC_GMS_MASK)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> GGC_GMS_OFST;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (igd_mode < 0xF0)</span><br><span style="color: hsl(120, 100%, 40%);">+ igd_mem_sz = igd_mode * 32 * (1024) * (1024);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ igd_mem_sz = 4 * (igd_mode - 0xF0 + 1) * (1024) * (1024);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return igd_mem_sz;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u32 sa_get_gtt_mem_sz(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *const root_dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 gtt_mode;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gtt_mem_sz = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!root_dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gtt_mode = (pci_read_config16(root_dev, GGC_REG) & GGC_GGMS_MASK)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> GGC_GGMS_OFST;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gtt_mode <= GGC_GGMS_8MB)</span><br><span style="color: hsl(120, 100%, 40%);">+ gtt_mem_sz = (1 << gtt_mode) * (1024) * (1024);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return gtt_mem_sz;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * SoC implementation</span><br><span> *</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27270">change 27270</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4 </div>
<div style="display:none"> Gerrit-Change-Number: 27270 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>