<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27295">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Get rid of unneeded whitespace<br><br>Change-Id: I3873cc8ff82cb043e4867a6fe8c1f253ab18714a<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/arch/arm/include/armv7/arch/cache.h<br>M src/arch/arm64/include/armv8/arch/cache.h<br>M src/device/dram/ddr3.c<br>M src/drivers/intel/gma/i915_reg.h<br>M src/lib/device_tree.c<br>M src/mainboard/amd/inagua/buildOpts.c<br>M src/mainboard/amd/parmer/buildOpts.c<br>M src/mainboard/lenovo/t400/devicetree.cb<br>M src/mainboard/msi/ms7721/buildOpts.c<br>M src/mainboard/pcengines/apu2/romstage.c<br>M src/southbridge/intel/ibexpeak/smi.c<br>11 files changed, 22 insertions(+), 22 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/27295/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h</span><br><span>index dd271c5..9a80217 100644</span><br><span>--- a/src/arch/arm/include/armv7/arch/cache.h</span><br><span>+++ b/src/arch/arm/include/armv7/arch/cache.h</span><br><span>@@ -48,8 +48,8 @@</span><br><span> #define SCTLR_SW (1 << 10) /* SWP and SWPB enable */</span><br><span> #define SCTLR_Z (1 << 11) /* Branch prediction enable */</span><br><span> #define SCTLR_I (1 << 12) /* Instruction cache enable */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SCTLR_V (1 << 13) /* Low/high exception vectors */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SCTLR_RR (1 << 14) /* Round Robin select */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCTLR_V (1 << 13) /* Low/high exception vectors */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCTLR_RR (1 << 14) /* Round Robin select */</span><br><span> /* Bits 16:15 are reserved */</span><br><span> #define SCTLR_HA (1 << 17) /* Hardware Access flag enable */</span><br><span> /* Bit 18 is reserved */</span><br><span>diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h</span><br><span>index b31c3b0..8e133ef 100644</span><br><span>--- a/src/arch/arm64/include/armv8/arch/cache.h</span><br><span>+++ b/src/arch/arm64/include/armv8/arch/cache.h</span><br><span>@@ -48,8 +48,8 @@</span><br><span> #define SCTLR_EL1_UMA (1 << 9) /* User mask access */</span><br><span> #define SCTLR_EL1_DZE (1 << 14) /* DC ZVA instruction at EL0 */</span><br><span> #define SCTLR_EL1_UCT (1 << 15) /* CTR_EL0 register EL0 access */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */</span><br><span> #define SCTLR_EL1_E0E (1 << 24) /* Exception endianness at EL0 */</span><br><span> #define SCTLR_EL1_UCI (1 << 26) /* EL0 access to cache instructions */</span><br><span> </span><br><span>diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c</span><br><span>index 535b48a..a084ca0 100644</span><br><span>--- a/src/device/dram/ddr3.c</span><br><span>+++ b/src/device/dram/ddr3.c</span><br><span>@@ -115,7 +115,7 @@</span><br><span> * array, and passed to this function.</span><br><span> *</span><br><span> * @param dimm pointer to @ref dimm_attr structure where the decoded data is to</span><br><span style="color: hsl(0, 100%, 40%);">- * be stored</span><br><span style="color: hsl(120, 100%, 40%);">+ * be stored</span><br><span> * @param spd array of raw data previously read from the SPD.</span><br><span> *</span><br><span> * @return @ref spd_status enumerator</span><br><span>@@ -123,7 +123,7 @@</span><br><span> * SPD_STATUS_INVALID -- invalid SPD or not a DDR3 SPD</span><br><span> * SPD_STATUS_CRC_ERROR -- CRC did not verify</span><br><span> * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was</span><br><span style="color: hsl(0, 100%, 40%);">- * detected.</span><br><span style="color: hsl(120, 100%, 40%);">+ * detected.</span><br><span> */</span><br><span> int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)</span><br><span> {</span><br><span>diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h</span><br><span>index ae774a5..d554874 100644</span><br><span>--- a/src/drivers/intel/gma/i915_reg.h</span><br><span>+++ b/src/drivers/intel/gma/i915_reg.h</span><br><span>@@ -242,9 +242,9 @@</span><br><span> #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)</span><br><span> #define MI_BATCH_NON_SECURE (1)</span><br><span> /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_BATCH_NON_SECURE_I965 (1<<8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_BATCH_NON_SECURE_I965 (1<<8)</span><br><span> #define MI_BATCH_PPGTT_HSW (1<<8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MI_BATCH_NON_SECURE_HSW (1<<13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MI_BATCH_NON_SECURE_HSW (1<<13)</span><br><span> #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)</span><br><span> #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */</span><br><span> #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */</span><br><span>diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c</span><br><span>index 2191659..3d44f39 100644</span><br><span>--- a/src/lib/device_tree.c</span><br><span>+++ b/src/lib/device_tree.c</span><br><span>@@ -497,12 +497,12 @@</span><br><span> *</span><br><span> * @param parent The node from which to start the relative path lookup.</span><br><span> * @param path An array of path component strings that will be looked</span><br><span style="color: hsl(0, 100%, 40%);">- * up in order to find the node. Must be terminated with</span><br><span style="color: hsl(0, 100%, 40%);">- * a NULL pointer. Example: {'firmware', 'coreboot', NULL}</span><br><span style="color: hsl(120, 100%, 40%);">+ * up in order to find the node. Must be terminated with</span><br><span style="color: hsl(120, 100%, 40%);">+ * a NULL pointer. Example: {'firmware', 'coreboot', NULL}</span><br><span> * @param addrcp Pointer that will be updated with any #address-cells</span><br><span style="color: hsl(0, 100%, 40%);">- * value found in the path. May be NULL to ignore.</span><br><span style="color: hsl(120, 100%, 40%);">+ * value found in the path. May be NULL to ignore.</span><br><span> * @param sizecp Pointer that will be updated with any #size-cells</span><br><span style="color: hsl(0, 100%, 40%);">- * value found in the path. May be NULL to ignore.</span><br><span style="color: hsl(120, 100%, 40%);">+ * value found in the path. May be NULL to ignore.</span><br><span> * @param create 1: Create node(s) if not found. 0: Return NULL instead.</span><br><span> * @return The found/created node, or NULL.</span><br><span> */</span><br><span>diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c</span><br><span>index ff947a0..1727e15 100644</span><br><span>--- a/src/mainboard/amd/inagua/buildOpts.c</span><br><span>+++ b/src/mainboard/amd/inagua/buildOpts.c</span><br><span>@@ -36,7 +36,7 @@</span><br><span> </span><br><span> /* Select the CPU socket type. */</span><br><span> #define INSTALL_G34_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#define INSTALL_C32_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_C32_SOCKET_SUPPORT FALSE</span><br><span> #define INSTALL_S1G3_SOCKET_SUPPORT FALSE</span><br><span> #define INSTALL_S1G4_SOCKET_SUPPORT FALSE</span><br><span> #define INSTALL_ASB2_SOCKET_SUPPORT FALSE</span><br><span>@@ -53,7 +53,7 @@</span><br><span> */</span><br><span> </span><br><span> #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE</span><br><span> #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE</span><br><span> #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c</span><br><span>index af2046d..c55cf2c 100644</span><br><span>--- a/src/mainboard/amd/parmer/buildOpts.c</span><br><span>+++ b/src/mainboard/amd/parmer/buildOpts.c</span><br><span>@@ -155,8 +155,8 @@</span><br><span> #if IS_ENABLED(CONFIG_GFXUMA)</span><br><span> #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED</span><br><span> #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED</span><br><span style="color: hsl(0, 100%, 40%);">-//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M</span><br><span> #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb</span><br><span>index 0c72c86..5945869 100644</span><br><span>--- a/src/mainboard/lenovo/t400/devicetree.cb</span><br><span>+++ b/src/mainboard/lenovo/t400/devicetree.cb</span><br><span>@@ -237,7 +237,7 @@</span><br><span> device pci 1f.3 on # SMBus</span><br><span> subsystemid 0x17aa 0x20f9</span><br><span> ioapic_irq 2 INTC 0x12</span><br><span style="color: hsl(0, 100%, 40%);">- # eeprom, 8 virtual devices, same chip</span><br><span style="color: hsl(120, 100%, 40%);">+ # eeprom, 8 virtual devices, same chip</span><br><span> chip drivers/i2c/at24rf08c</span><br><span> device i2c 54 on end</span><br><span> device i2c 55 on end</span><br><span>diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c</span><br><span>index adcb417..f160745 100644</span><br><span>--- a/src/mainboard/msi/ms7721/buildOpts.c</span><br><span>+++ b/src/mainboard/msi/ms7721/buildOpts.c</span><br><span>@@ -170,8 +170,8 @@</span><br><span> #if IS_ENABLED(CONFIG_GFXUMA)</span><br><span> #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED</span><br><span> #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED</span><br><span style="color: hsl(0, 100%, 40%);">-//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/</span><br><span style="color: hsl(0, 100%, 40%);">-#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M</span><br><span> #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c</span><br><span>index 093cad6..7ea89b8 100644</span><br><span>--- a/src/mainboard/pcengines/apu2/romstage.c</span><br><span>+++ b/src/mainboard/pcengines/apu2/romstage.c</span><br><span>@@ -74,8 +74,8 @@</span><br><span> </span><br><span> /* Load MPB */</span><br><span> val = cpuid_eax(1);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);</span><br><span> </span><br><span> post_code(0x37);</span><br><span> AGESAWRAPPER(amdinitreset);</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c</span><br><span>index 9f6badb..10e2fa6 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/smi.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/smi.c</span><br><span>@@ -325,7 +325,7 @@</span><br><span> reset_pm1_status();</span><br><span> </span><br><span> /* Set EOS bit so other SMIs can occur. */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_set_eos();</span><br><span style="color: hsl(120, 100%, 40%);">+ smi_set_eos();</span><br><span> }</span><br><span> </span><br><span> void smm_setup_structures(void *gnvs, void *tcg, void *smi1)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27295">change 27295</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27295"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3873cc8ff82cb043e4867a6fe8c1f253ab18714a </div>
<div style="display:none"> Gerrit-Change-Number: 27295 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>