<p>Aamir Bohra has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27262">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/common/block/systemagent: Add provision to configure PCIEXBAR from soc<br><br>This implementation adds provision to configure SOC specific PCIEXBAR.<br><br>Change-Id: I89b0e9c927d395ac6d27201e0b3a8658e958518a<br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>---<br>M src/soc/intel/apollolake/Kconfig<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/common/block/systemagent/Kconfig<br>M src/soc/intel/common/block/systemagent/systemagent_early.c<br>M src/soc/intel/denverton_ns/Kconfig<br>M src/soc/intel/skylake/Kconfig<br>6 files changed, 28 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/27262/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig</span><br><span>index 4577e76..a172e43 100644</span><br><span>--- a/src/soc/intel/apollolake/Kconfig</span><br><span>+++ b/src/soc/intel/apollolake/Kconfig</span><br><span>@@ -133,6 +133,12 @@</span><br><span> bool</span><br><span> default y</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config MMCONF_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xe0000000</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This option allows you to select MMIO Base Address of PCI Express.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config PCR_BASE_ADDRESS</span><br><span> hex</span><br><span> default 0xd0000000</span><br><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index 101d71e..1f9316e 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -161,6 +161,12 @@</span><br><span> hex</span><br><span> default 0x200000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config MMCONF_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xe0000000</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This option allows you to select MMIO Base Address of PCI Express.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config PCR_BASE_ADDRESS</span><br><span> hex</span><br><span> default 0xfd000000</span><br><span>diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig</span><br><span>index 1222573..d7619a0 100644</span><br><span>--- a/src/soc/intel/common/block/systemagent/Kconfig</span><br><span>+++ b/src/soc/intel/common/block/systemagent/Kconfig</span><br><span>@@ -3,10 +3,6 @@</span><br><span> help</span><br><span> Intel Processor common System Agent support</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config MMCONF_BASE_ADDRESS</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0xe0000000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config SA_PCIEX_LENGTH</span><br><span> hex</span><br><span> default 0x10000000 if (PCIEX_LENGTH_256MB)</span><br><span>diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c</span><br><span>index 609e159..1c13e17 100644</span><br><span>--- a/src/soc/intel/common/block/systemagent/systemagent_early.c</span><br><span>+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c</span><br><span>@@ -24,6 +24,10 @@</span><br><span> #include "systemagent_def.h"</span><br><span> #include <timer.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if !defined(CONFIG_MMCONF_BASE_ADDRESS) || !CONFIG_MMCONF_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+#error "PCI Express MMIO base address (PCIEXBAR) needs to be non-zero!"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #if !ENV_RAMSTAGE</span><br><span> void bootblock_systemagent_early_init(void)</span><br><span> {</span><br><span>diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig</span><br><span>index 6c366f1..236b06c 100644</span><br><span>--- a/src/soc/intel/denverton_ns/Kconfig</span><br><span>+++ b/src/soc/intel/denverton_ns/Kconfig</span><br><span>@@ -90,6 +90,12 @@</span><br><span> int</span><br><span> default 16</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config MMCONF_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xe0000000</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This option allows you to select MMIO Base Address of PCI Express.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config PCR_BASE_ADDRESS</span><br><span> hex</span><br><span> default 0xfd000000</span><br><span>diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig</span><br><span>index 3e0158b..b193e07 100644</span><br><span>--- a/src/soc/intel/skylake/Kconfig</span><br><span>+++ b/src/soc/intel/skylake/Kconfig</span><br><span>@@ -154,6 +154,12 @@</span><br><span> hex</span><br><span> default 0x400000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config MMCONF_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xe0000000</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This option allows you to select MMIO Base Address of PCI Express.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config PCR_BASE_ADDRESS</span><br><span> hex</span><br><span> default 0xfd000000</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27262">change 27262</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27262"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I89b0e9c927d395ac6d27201e0b3a8658e958518a </div>
<div style="display:none"> Gerrit-Change-Number: 27262 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>