<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27250">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block/pmc: Get rid of pmc_fixup_power_state<br><br>Now that APL does not need pmc_fixup_power_state, this function can be<br>removed from the PMC common code as well.<br><br>BUG=b:110836465<br><br>Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be<br>Signed-off-by: Furquan Shaikh <furquan@google.com><br>---<br>M src/soc/intel/common/block/include/intelblocks/pmclib.h<br>M src/soc/intel/common/block/pmc/pmclib.c<br>2 files changed, 0 insertions(+), 27 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27250/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h</span><br><span>index d631f01..ddf384b 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h</span><br><span>@@ -150,9 +150,6 @@</span><br><span>  */</span><br><span> void pmc_global_reset_lock(void);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Rewrite the gpe0 registers in cbmem to proper values as per routing table */</span><br><span style="color: hsl(0, 100%, 40%);">-void pmc_fixup_power_state(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Returns the power state structure */</span><br><span> struct chipset_power_state *pmc_get_power_state(void);</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>index 38d4196..0795990 100644</span><br><span>--- a/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>+++ b/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>@@ -385,30 +385,6 @@</span><br><span>  return soc_prev_sleep_state(ps, prev_sleep_state);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This function re-writes the gpe0 register values in power state</span><br><span style="color: hsl(0, 100%, 40%);">- * cbmem variable. After system wakes from sleep state internal PMC logic</span><br><span style="color: hsl(0, 100%, 40%);">- * writes default values in GPE_CFG register which gives a wrong offset to</span><br><span style="color: hsl(0, 100%, 40%);">- * calculate the wake reason. So we need to set it again to the routing</span><br><span style="color: hsl(0, 100%, 40%);">- * table as per the devicetree.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-void pmc_fixup_power_state(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-    int i;</span><br><span style="color: hsl(0, 100%, 40%);">-  struct chipset_power_state *ps;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- ps = pmc_get_power_state();</span><br><span style="color: hsl(0, 100%, 40%);">-     if (ps == NULL)</span><br><span style="color: hsl(0, 100%, 40%);">-         return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < GPE0_REG_MAX; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">-         ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i));</span><br><span style="color: hsl(0, 100%, 40%);">-              ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i));</span><br><span style="color: hsl(0, 100%, 40%);">-                printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",</span><br><span style="color: hsl(0, 100%, 40%);">-                 i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);</span><br><span style="color: hsl(0, 100%, 40%);">-    }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void pmc_fill_pm_reg_info(struct chipset_power_state *ps)</span><br><span> {</span><br><span>         int i;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27250">change 27250</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27250"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be </div>
<div style="display:none"> Gerrit-Change-Number: 27250 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>