<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27244">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/sandybridge: Don't use PCI operations on the pci_domain device<br><br>The pci_domain just happens to have bus, device and function set to 0,<br>which is why to code works.<br><br>This patch still keeps adding the fixed resources in the pci_domain<br>ops since moving it to the PCI ops which could properly use the<br>function argument for PCI operations would require all PCI IDs to be<br>added or else breakages are to be expected.<br><br>Change-Id: Id73c16fad4fb9ece78595844a39da993d169f057<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/sandybridge/northbridge.c<br>1 file changed, 11 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/27244/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c</span><br><span>index 8c2aaf3..56d3c49 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/northbridge.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/northbridge.c</span><br><span>@@ -152,26 +152,28 @@</span><br><span>    * 14fe00000   5368MB TOUUD</span><br><span>   */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+       struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>    /* Top of Upper Usable DRAM, including remap */</span><br><span style="color: hsl(0, 100%, 40%);">- touud = pci_read_config32(dev, TOUUD+4);</span><br><span style="color: hsl(120, 100%, 40%);">+      touud = pci_read_config32(mch, TOUUD+4);</span><br><span>     touud <<= 32;</span><br><span style="color: hsl(0, 100%, 40%);">-     touud |= pci_read_config32(dev, TOUUD);</span><br><span style="color: hsl(120, 100%, 40%);">+       touud |= pci_read_config32(mch, TOUUD);</span><br><span> </span><br><span>  /* Top of Lower Usable DRAM */</span><br><span style="color: hsl(0, 100%, 40%);">-  tolud = pci_read_config32(dev, TOLUD);</span><br><span style="color: hsl(120, 100%, 40%);">+        tolud = pci_read_config32(mch, TOLUD);</span><br><span> </span><br><span>   /* Top of Memory - does not account for any UMA */</span><br><span style="color: hsl(0, 100%, 40%);">-      tom = pci_read_config32(dev, 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+   tom = pci_read_config32(mch, 0xa4);</span><br><span>  tom <<= 32;</span><br><span style="color: hsl(0, 100%, 40%);">-       tom |= pci_read_config32(dev, 0xa0);</span><br><span style="color: hsl(120, 100%, 40%);">+  tom |= pci_read_config32(mch, 0xa0);</span><br><span> </span><br><span>     printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",</span><br><span>              touud, tolud, tom);</span><br><span> </span><br><span>       /* ME UMA needs excluding if total memory <4GB */</span><br><span style="color: hsl(0, 100%, 40%);">-    me_base = pci_read_config32(dev, 0x74);</span><br><span style="color: hsl(120, 100%, 40%);">+       me_base = pci_read_config32(mch, 0x74);</span><br><span>      me_base <<= 32;</span><br><span style="color: hsl(0, 100%, 40%);">-   me_base |= pci_read_config32(dev, 0x70);</span><br><span style="color: hsl(120, 100%, 40%);">+      me_base |= pci_read_config32(mch, 0x70);</span><br><span> </span><br><span>         printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base);</span><br><span> </span><br><span>@@ -190,7 +192,7 @@</span><br><span>  }</span><br><span> </span><br><span>        /* Graphics memory comes next */</span><br><span style="color: hsl(0, 100%, 40%);">-        ggc = pci_read_config16(dev, GGC);</span><br><span style="color: hsl(120, 100%, 40%);">+    ggc = pci_read_config16(mch, GGC);</span><br><span>   if (!(ggc & 2)) {</span><br><span>                printk(BIOS_DEBUG, "IGD decoded, subtracting ");</span><br><span> </span><br><span>@@ -210,7 +212,7 @@</span><br><span>         }</span><br><span> </span><br><span>        /* Calculate TSEG size from its base which must be below GTT */</span><br><span style="color: hsl(0, 100%, 40%);">- tseg_base = pci_read_config32(dev, 0xb8);</span><br><span style="color: hsl(120, 100%, 40%);">+     tseg_base = pci_read_config32(mch, 0xb8);</span><br><span>    uma_size = (uma_memory_base - tseg_base) >> 10;</span><br><span>        tomk -= uma_size;</span><br><span>    uma_memory_base = tomk * 1024ULL;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27244">change 27244</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id73c16fad4fb9ece78595844a39da993d169f057 </div>
<div style="display:none"> Gerrit-Change-Number: 27244 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>