<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27243">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/pineview: Don't use PCI operations on the pci_domain device<br><br>The pci_domain just happens to have bus, device and function set to 0,<br>which is why to code works.<br><br>This patch still keeps adding the fixed resources in the pci_domain<br>ops since moving it to the PCI ops which could properly use the<br>function argument for PCI operations would require all PCI IDs to be<br>added or else breakages are to be expected.<br><br>Change-Id: Iea5a09c62cca102b2c211e9256295c24cf3e9fa0<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/pineview/northbridge.c<br>1 file changed, 9 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/27243/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c</span><br><span>index 93c7558..6b8075e 100644</span><br><span>--- a/src/northbridge/intel/pineview/northbridge.c</span><br><span>+++ b/src/northbridge/intel/pineview/northbridge.c</span><br><span>@@ -59,20 +59,22 @@</span><br><span>        u16 index;</span><br><span>   const u32 top32memk = 4 * (GiB / KiB);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+    struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>    index = 3;</span><br><span> </span><br><span>       pci_domain_read_resources(dev);</span><br><span> </span><br><span>  /* Top of Upper Usable DRAM, including remap */</span><br><span style="color: hsl(0, 100%, 40%);">- touud = pci_read_config16(dev, TOUUD);</span><br><span style="color: hsl(120, 100%, 40%);">+        touud = pci_read_config16(mch, TOUUD);</span><br><span>       touud <<= 20;</span><br><span> </span><br><span>      /* Top of Lower Usable DRAM */</span><br><span style="color: hsl(0, 100%, 40%);">-  tolud = pci_read_config16(dev, TOLUD) & 0xfff0;</span><br><span style="color: hsl(120, 100%, 40%);">+   tolud = pci_read_config16(mch, TOLUD) & 0xfff0;</span><br><span>  tolud <<= 16;</span><br><span> </span><br><span>      /* Top of Memory - does not account for any UMA */</span><br><span style="color: hsl(0, 100%, 40%);">-      tom = pci_read_config16(dev, TOM) & 0x1ff;</span><br><span style="color: hsl(120, 100%, 40%);">+        tom = pci_read_config16(mch, TOM) & 0x1ff;</span><br><span>       tom <<= 27;</span><br><span> </span><br><span>        printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ",</span><br><span>@@ -81,7 +83,7 @@</span><br><span>    tomk = tolud >> 10;</span><br><span> </span><br><span>        /* Graphics memory */</span><br><span style="color: hsl(0, 100%, 40%);">-   const u16 ggc = pci_read_config16(dev, GGC);</span><br><span style="color: hsl(120, 100%, 40%);">+  const u16 ggc = pci_read_config16(mch, GGC);</span><br><span>         const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);</span><br><span>    printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10);</span><br><span>      tomk -= gms_sizek;</span><br><span>@@ -91,9 +93,9 @@</span><br><span>       printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);</span><br><span>       tomk -= gsm_sizek;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-  const u32 tseg_basek = pci_read_config32(dev, TSEG) >> 10;</span><br><span style="color: hsl(0, 100%, 40%);">-        const u32 igd_basek = pci_read_config32(dev, GBSM) >> 10;</span><br><span style="color: hsl(0, 100%, 40%);">- const u32 gtt_basek = pci_read_config32(dev, BGSM) >> 10;</span><br><span style="color: hsl(120, 100%, 40%);">+       const u32 tseg_basek = pci_read_config32(mch, TSEG) >> 10;</span><br><span style="color: hsl(120, 100%, 40%);">+      const u32 igd_basek = pci_read_config32(mch, GBSM) >> 10;</span><br><span style="color: hsl(120, 100%, 40%);">+       const u32 gtt_basek = pci_read_config32(mch, BGSM) >> 10;</span><br><span> </span><br><span>  /* Subtract TSEG size */</span><br><span>     tseg_sizek = gtt_basek - tseg_basek;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27243">change 27243</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27243"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iea5a09c62cca102b2c211e9256295c24cf3e9fa0 </div>
<div style="display:none"> Gerrit-Change-Number: 27243 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>