<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27242">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/gm45: Don't use PCI operations on the pci_domain device<br><br>The pci_domain just happens to have bus, device and function set to 0,<br>which is why to code works.<br><br>This patch still keeps adding the fixed resources in the pci_domain<br>ops since moving it to the PCI ops which could properly use the<br>function argument for PCI operations would require all PCI IDs to be<br>added or else breakages are to be expected.<br><br>Change-Id: I598b056d5fb1ce23b390b2f0ab4e9fb242d3685a<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/gm45/northbridge.c<br>1 file changed, 11 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27242/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c</span><br><span>index 4c42513..a3f517b 100644</span><br><span>--- a/src/northbridge/intel/gm45/northbridge.c</span><br><span>+++ b/src/northbridge/intel/gm45/northbridge.c</span><br><span>@@ -95,16 +95,18 @@</span><br><span> </span><br><span>   pci_domain_read_resources(dev);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+   struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>    /* Top of Upper Usable DRAM, including remap */</span><br><span style="color: hsl(0, 100%, 40%);">- touud = pci_read_config16(dev, D0F0_TOUUD);</span><br><span style="color: hsl(120, 100%, 40%);">+   touud = pci_read_config16(mch, D0F0_TOUUD);</span><br><span>  touud <<= 20;</span><br><span> </span><br><span>      /* Top of Lower Usable DRAM */</span><br><span style="color: hsl(0, 100%, 40%);">-  tolud = pci_read_config16(dev, D0F0_TOLUD) & 0xfff0;</span><br><span style="color: hsl(120, 100%, 40%);">+      tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0;</span><br><span>     tolud <<= 16;</span><br><span> </span><br><span>      /* Top of Memory - does not account for any UMA */</span><br><span style="color: hsl(0, 100%, 40%);">-      tom = pci_read_config16(dev, D0F0_TOM) & 0x1ff;</span><br><span style="color: hsl(120, 100%, 40%);">+   tom = pci_read_config16(mch, D0F0_TOM) & 0x1ff;</span><br><span>  tom <<= 27;</span><br><span> </span><br><span>        printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",</span><br><span>@@ -113,7 +115,7 @@</span><br><span>         tomk = tolud >> 10;</span><br><span> </span><br><span>        /* Graphics memory comes next */</span><br><span style="color: hsl(0, 100%, 40%);">-        const u16 ggc = pci_read_config16(dev, D0F0_GGC);</span><br><span style="color: hsl(120, 100%, 40%);">+     const u16 ggc = pci_read_config16(mch, D0F0_GGC);</span><br><span>    if (!(ggc & 2)) {</span><br><span>                printk(BIOS_DEBUG, "IGD decoded, subtracting ");</span><br><span> </span><br><span>@@ -129,7 +131,7 @@</span><br><span> </span><br><span>             uma_sizek = gms_sizek + gsm_sizek;</span><br><span>   }</span><br><span style="color: hsl(0, 100%, 40%);">-       const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);</span><br><span style="color: hsl(120, 100%, 40%);">+       const u8 esmramc = pci_read_config8(mch, D0F0_ESMRAMC);</span><br><span>      const u32 tseg_sizek = decode_tseg_size(esmramc);</span><br><span>    printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10);</span><br><span>     tomk -= tseg_sizek;</span><br><span>@@ -185,10 +187,12 @@</span><br><span> {</span><br><span>     u32 reg32;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+        struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>    /* Enable SERR */</span><br><span style="color: hsl(0, 100%, 40%);">-       reg32 = pci_read_config32(dev, PCI_COMMAND);</span><br><span style="color: hsl(120, 100%, 40%);">+  reg32 = pci_read_config32(mch, PCI_COMMAND);</span><br><span>         reg32 |= PCI_COMMAND_SERR;</span><br><span style="color: hsl(0, 100%, 40%);">-      pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+  pci_write_config32(mch, PCI_COMMAND, reg32);</span><br><span> }</span><br><span> </span><br><span> static struct device_operations pci_domain_ops = {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27242">change 27242</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http: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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I598b056d5fb1ce23b390b2f0ab4e9fb242d3685a </div>
<div style="display:none"> Gerrit-Change-Number: 27242 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>