<p><a href="https://review.coreboot.org/27171">View Change</a></p><p>162 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c">File src/mainboard/google/octopus/variants/phaser/gpio.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@29">Patch Set #1, Line 29:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@30">Patch Set #1, Line 30:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TRST_L */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@31">Patch Set #1, Line 31:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TMS */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@32">Patch Set #1, Line 32:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDI */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@33">Patch Set #1, Line 33:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDO */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@34">Patch Set #1, Line 34:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TP_GPIO5 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@35">Patch Set #1, Line 35:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PREQ_L */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@36">Patch Set #1, Line 36:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PRDY_L */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@37">Patch Set #1, Line 37:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK0 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@38">Patch Set #1, Line 38:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_0 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@39">Patch Set #1, Line 39:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_1 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@40">Patch Set #1, Line 40:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_2 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@41">Patch Set #1, Line 41:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_3 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@42">Patch Set #1, Line 42:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_4 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@43">Patch Set #1, Line 43:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_5 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@44">Patch Set #1, Line 44:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_6 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@45">Patch Set #1, Line 45:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_7*/</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@46">Patch Set #1, Line 46:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_17, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK_1 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@47">Patch Set #1, Line 47:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_18, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_8 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@48">Patch Set #1, Line 48:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_19, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_9 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@49">Patch Set #1, Line 49:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_20, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_10 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@51">Patch Set #1, Line 51:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNVI_MFUART2_TXD_PTI_12 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@52">Patch Set #1, Line 52:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNVI_GNSS_PA_BLANKING_PTI_13 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@53">Patch Set #1, Line 53:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_24, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_14 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@54">Patch Set #1, Line 54:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_25, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_15 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@55">Patch Set #1, Line 55:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_CLK2 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@56">Patch Set #1, Line 56:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_16 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@57">Patch Set #1, Line 57:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_28, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_17 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@58">Patch Set #1, Line 58:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_29, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_18 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@59">Patch Set #1, Line 59:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_30, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_19 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@60">Patch Set #1, Line 60:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_31, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_20 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@61">Patch Set #1, Line 61:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_32, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_21 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@62">Patch Set #1, Line 62:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_33, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_22 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@63">Patch Set #1, Line 63:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_34, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_23 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@64">Patch Set #1, Line 64:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_35, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DCI_CLK_PTICLK3 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@65">Patch Set #1, Line 65:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DCI_DATA_PTITRACE3_0 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@66">Patch Set #1, Line 66:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_1 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@67">Patch Set #1, Line 67:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_2 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@68">Patch Set #1, Line 68:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_3 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@69">Patch Set #1, Line 69:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_4 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@70">Patch Set #1, Line 70:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_5 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@71">Patch Set #1, Line 71:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_42, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_WIFI_RST_N -- TP135 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@72">Patch Set #1, Line 72:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@73">Patch Set #1, Line 73:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_A_OC_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@74">Patch Set #1, Line 74:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_C_OC_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@75">Patch Set #1, Line 75:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_46, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_PCH_GPIO46 -- TP37 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@76">Patch Set #1, Line 76:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_47, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_PCH_GPIO47 -- TP31 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@77">Patch Set #1, Line 77:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PCH_PMIC_I2C_SDA */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@78">Patch Set #1, Line 78:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PCH_PMIC_I2C_SCL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@79">Patch Set #1, Line 79:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SDA */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@80">Patch Set #1, Line 80:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SCL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@81">Patch Set #1, Line 81:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_52, NONE, DEEP, HIZCRx0, DISPUPD), /* PCH_I2C_P_SENSOR_SDA */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@82">Patch Set #1, Line 82:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_53, NONE, DEEP, HIZCRx0, DISPUPD), /* PCH_I2C_P_SENSOR_SCL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@85">Patch Set #1, Line 85:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* DBG_PCH_I2C_SDA */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@86">Patch Set #1, Line 86:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* DBG_PCH_I2C_SCL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@87">Patch Set #1, Line 87:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_58, NONE, DEEP, HIZCRx0, DISPUPD), /* PCH_I2C_H1_SDA */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@88">Patch Set #1, Line 88:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_59, NONE, DEEP, HIZCRx0, DISPUPD), /* PCH_I2C_H1_SCL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@89">Patch Set #1, Line 89:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* PCHRX_MIPI60TX_UART */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@90">Patch Set #1, Line 90:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* PCHTX_MIPI60RX_UART */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@92">Patch Set #1, Line 92:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@93">Patch Set #1, Line 93:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* PCHRX_UART2 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@94">Patch Set #1, Line 94:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* PCHTX_UART2 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@96">Patch Set #1, Line 96:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_67, NONE, DEEP, HIZCRx0, DISPUPD), /* EN_PP3300_DX_LTE_SOC -- TP45 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@103">Patch Set #1, Line 103:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_L */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@104">Patch Set #1, Line 104:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCH_PROCHOT_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@105">Patch Set #1, Line 105:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_211, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_RST_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@106">Patch Set #1, Line 106:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* TOUCHSCREEN_INT_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@107">Patch Set #1, Line 107:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@108">Patch Set #1, Line 108:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_214, NONE, DEEP, HIZCRx0, DISPUPD), /* P_SENSOR_INT_L -- TP69 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@113">Patch Set #1, Line 113:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_76, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_PCH_GPIO_76 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@114">Patch Set #1, Line 114:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_77, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_PCH_GPIO_77 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@115">Patch Set #1, Line 115:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_78, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_PCH_GPIO_78 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@120">Patch Set #1, Line 120:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), /* GPIO_81_DEBUG (Boot halt) -- MIPI60 DEBUG */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@131">Patch Set #1, Line 131:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, DN_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCH_SPI_CS0_L */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@132">Patch Set #1, Line 132:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@133">Patch Set #1, Line 133:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_SPI_MOSI */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@134">Patch Set #1, Line 134:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_SPI_MISO_R */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@135">Patch Set #1, Line 135:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_94, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO2 - unused */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@136">Patch Set #1, Line 136:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_95, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO3 - unused */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@137">Patch Set #1, Line 137:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* PCH_SPI_CLK */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@140">Patch Set #1, Line 140:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PLT_RST_L */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@141">Patch Set #1, Line 141:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, UP_20K, DEEP, NF1, TxDRxE, ENPU),/* EC_PCH_PWR_BTN_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@142">Patch Set #1, Line 142:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PCH_SLP_S0_L */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@143">Patch Set #1, Line 143:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PCH_SLP_S3_L */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@144">Patch Set #1, Line 144:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PCH_SLP_S4_L */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@146">Patch Set #1, Line 146:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_104, NONE, DEEP, HIZCRx0, DISPUPD),/* EN_PP3300_EMMC -- TP30 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@147">Patch Set #1, Line 147:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* TOUCHSCREEN_RST */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@148">Patch Set #1, Line 148:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PMU_BATLOW_L */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@149">Patch Set #1, Line 149:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* SYS_RST_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@151">Patch Set #1, Line 151:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD),/* SUS_STAT_B -- BT_DISABLE_L */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@154">Patch Set #1, Line 154:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_AUDIO_SDA_Q */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@155">Patch Set #1, Line 155:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_AUDIO_SCL_Q */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@158">Patch Set #1, Line 158:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_TRACKPAD_SDA */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@159">Patch Set #1, Line 159:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_TRACKPAD_SCL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@162">Patch Set #1, Line 162:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_TOUCHSCREEN_SDA */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@163">Patch Set #1, Line 163:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_TOUCHSCREEN_SCL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@167">Patch Set #1, Line 167:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_117, NONE, DEEP, HIZCRx0, DISPUPD),/* LTE_WAKE_L -- TP80 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@169">Patch Set #1, Line 169:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* WLAN_PCIE_WAKE_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@172">Patch Set #1, Line 172:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_120, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_CLKREQ0_ODL -- TP157 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@173">Patch Set #1, Line 173:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_121, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_CLKREQ1_ODL -- TP145 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@174">Patch Set #1, Line 174:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_122, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_CLKREQ2_ODL -- TP171 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@175">Patch Set #1, Line 175:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, UP_20K, DEEP, NF1, TxDRxE, DISPUPD), /* WLAN_PCIE_CLKREQ_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@178">Patch Set #1, Line 178:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_124, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SDA -- unused */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@179">Patch Set #1, Line 179:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_125, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SCL -- unused */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@180">Patch Set #1, Line 180:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_126, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SDA -- unused */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@181">Patch Set #1, Line 181:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_127, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SCL -- unused */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@184">Patch Set #1, Line 184:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* EN_PP3300_EDP_DX */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@185">Patch Set #1, Line 185:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* SOC_EDP_BKLTEN */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@186">Patch Set #1, Line 186:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* SOC_EDP_BKLTCTL_1V8 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@189">Patch Set #1, Line 189:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* USB_C0_HPD_1V8_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@190">Patch Set #1, Line 190:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* USB_C1_HPD_1V8_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@191">Patch Set #1, Line 191:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* EDP_HPD_PANEL_1V8_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@194">Patch Set #1, Line 194:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@195">Patch Set #1, Line 195:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@196">Patch Set #1, Line 196:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@197">Patch Set #1, Line 197:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@198">Patch Set #1, Line 198:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_INT_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@199">Patch Set #1, Line 199:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@200">Patch Set #1, Line 200:</a> <code style="font-family:monospace,monospace"> // TODO check if it is ok to set to GPIROUTSCI (as in Coral/Reef and others).</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@203">Patch Set #1, Line 203:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPI_SCI_IOS(GPIO_141, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/* GPIO_141 -- EC_PCH_WAKE_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@204">Patch Set #1, Line 204:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@205">Patch Set #1, Line 205:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_143, NONE, DEEP, HIZCRx0, DISPUPD),/* LTE_SAR_ODL -- TP64 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@206">Patch Set #1, Line 206:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_144, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_GPIO_144 -- TP49 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@207">Patch Set #1, Line 207:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_145, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_GPIO_145 -- TP7 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@218">Patch Set #1, Line 218:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S0_SCLK_R -- TP53 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@219">Patch Set #1, Line 219:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S0_SFRM_R -- TP54 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@220">Patch Set #1, Line 220:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S0_PCH_RX -- TP57 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@221">Patch Set #1, Line 221:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_160, NONE, DEEP, HIZCRx0, DISPUPD), /* I2S0_PCH_TX -- TP59 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@222">Patch Set #1, Line 222:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_161, NONE, DEEP, HIZCRx0, DISPUPD), /* LTE_OFF_ODL -- TP65 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@223">Patch Set #1, Line 223:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S_SCLK_SPKR */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@224">Patch Set #1, Line 224:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S_SFRM_SPKR */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@226">Patch Set #1, Line 226:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S_PCH_TX_SPKR_RX */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@227">Patch Set #1, Line 227:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, SAME), /* I2S2_SCLK_R */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@228">Patch Set #1, Line 228:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* I2S2_SFRM_R */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@229">Patch Set #1, Line 229:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* I2S2_PCH_RX */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@230">Patch Set #1, Line 230:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* I2S2_PCH_TX */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@231">Patch Set #1, Line 231:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* I2S2_MCLK_R */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@232">Patch Set #1, Line 232:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_171, DN_20K, DEEP, NF1), /* AVS_M_CLK_A1 -- DMIC_CLK1_R */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@233">Patch Set #1, Line 233:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_CLK_B1 -- DMIC_CLK2_R */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@234">Patch Set #1, Line 234:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_173, DN_20K, DEEP, NF1), /* AVS_M_DATA_1 -- DMIC_DATA_R */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@235">Patch Set #1, Line 235:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_174, NONE, DEEP, HIZCRx0, DISPUPD), /* AVS_M_CLK_AB2 -- TP_GPIO_174 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@236">Patch Set #1, Line 236:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE(GPIO_175, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_2 -- DMIC_CAM2_DATA */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@239">Patch Set #1, Line 239:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_176, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* TP_SMB_ALERT_N */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@240">Patch Set #1, Line 240:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_177, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_PCH_SMB_CLK -- TP160 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@242">Patch Set #1, Line 242:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_189, 0, DEEP, NONE, TxDRxE, DISPUPD), /* EC_IN_RW_OD */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@243">Patch Set #1, Line 243:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNVI_BRI_DT_R */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@244">Patch Set #1, Line 244:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNVI_BRI_RSP */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@245">Patch Set #1, Line 245:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNVI_RGI_DT_R */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@246">Patch Set #1, Line 246:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@247">Patch Set #1, Line 247:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNVI_RF_RESET_L */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@248">Patch Set #1, Line 248:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPU), /* EMMC_CLK */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@249">Patch Set #1, Line 249:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT0 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@250">Patch Set #1, Line 250:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT1 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@251">Patch Set #1, Line 251:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT2 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@252">Patch Set #1, Line 252:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT3 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@253">Patch Set #1, Line 253:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT4 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@254">Patch Set #1, Line 254:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT5 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@255">Patch Set #1, Line 255:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT6 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@256">Patch Set #1, Line 256:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT7 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@257">Patch Set #1, Line 257:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_CMD */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@258">Patch Set #1, Line 258:</a> <code style="font-family:monospace,monospace"> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0, ENPU), /* EMMC_RCLK */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27171/1/src/mainboard/google/octopus/variants/phaser/gpio.c@259">Patch Set #1, Line 259:</a> <code style="font-family:monospace,monospace"> PAD_CFG_GPIO_HI_Z(GPIO_210, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_GPIO210 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/27171">change 27171</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: comment </div>
<div style="display:none"> Gerrit-Change-Id: If5777a98d21df7a30503ada24c7000994aa4c3de </div>
<div style="display:none"> Gerrit-Change-Number: 27171 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nick Chen <nickchen@ami.corp-partner.google.com> </div>
<div style="display:none"> Gerrit-CC: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-Comment-Date: Wed, 20 Jun 2018 09:50:05 +0000 </div>
<div style="display:none"> Gerrit-HasComments: Yes </div>
<div style="display:none"> Gerrit-HasLabels: No </div>