<p><a href="https://review.coreboot.org/27168">View Change</a></p><p>5 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27168/1//COMMIT_MSG">Commit Message:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27168/1//COMMIT_MSG@9">Patch Set #1, Line 9:</a> <code style="font-family:monospace,monospace">ICH8</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">ICH was the predecessor of the PCH. Because some features of<br>the GMCH (northbridge) also moved into the PCH Intel counts<br>the PCH series based on the GMCH numbers. i.e. after 4 series<br>GMCH came 5 series PCH. This is about the 8 series PCHs.</p><p style="white-space: pre-wrap; word-wrap: break-word;">Also, please break lines before 72 characters.</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27168/1//COMMIT_MSG@12">Patch Set #1, Line 12:</a> <code style="font-family:monospace,monospace">Documentation on the PCH can be found here:</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Please separate paragraphs with an empty line.</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27168/1//COMMIT_MSG@13">Patch Set #1, Line 13:</a> <code style="font-family:monospace,monospace">https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/8-series-chipset-pch-datasheet.pdf</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">No links please. Document and revision numbers are more useful<br>in the long run.</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27168/1/util/inteltool/gpio.c">File util/inteltool/gpio.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27168/1/util/inteltool/gpio.c@866">Patch Set #1, Line 866:</a> <code style="font-family:monospace,monospace"> case PCI_DEVICE_ID_INTEL_H81:</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">According to the datasheet the non-LP version doesn't have the<br>registers above 0x68. Can you confirm if you see (or don't see)<br>valid values above that?</p><p style="white-space: pre-wrap; word-wrap: break-word;">In case, you can still use the same register description, just<br>reduce the `size` below.</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27168/1/util/inteltool/inteltool.c">File util/inteltool/inteltool.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27168/1/util/inteltool/inteltool.c@235">Patch Set #1, Line 235:</a> </p><p><blockquote style="border-left: 1px solid #aaa; margin: 10px 0; padding: 0 10px;"><pre style="font-family: monospace,monospace; white-space: pre-wrap;"> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_MOBILE,<br> "Intel(R) C8 Mobile"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_DESKTOP,<br> "Intel(R) C8 Desktop"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z87,<br> "Intel(R) Z87"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z85,<br> "Intel(R) Z85"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM86,<br> "Intel(R) HM86"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H87,<br> "Intel(R) H87"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM87,<br> "Intel(R) HM87"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q85,<br> "Intel(R) Q85"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q87,<br> "Intel(R) Q87"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM87,<br> "Intel(R) QM87"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B85,<br> "Intel(R) B85"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C222,<br> "Intel(R) C222"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224,<br> "Intel(R) C224"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226,<br> "Intel(R) C226"},<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81,<br> "Intel(R) H81"},<br></pre></blockquote></p><p style="white-space: pre-wrap; word-wrap: break-word;">Please don't break lines that fit into 80 chars.</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/27168">change 27168</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27168"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
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<div style="display:none"> Gerrit-Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35 </div>
<div style="display:none"> Gerrit-Change-Number: 27168 </div>
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<div style="display:none"> Gerrit-Owner: Quan Tran <qeed.quan@gmail.com> </div>
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<div style="display:none"> Gerrit-Comment-Date: Wed, 20 Jun 2018 11:33:36 +0000 </div>
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