<p>Philipp Deppenwiese <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/27150">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
David Hendricks: Looks good to me, approved
Philipp Deppenwiese: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Documentation: Add cavium SoC and mainboard<br><br>* Add documentation for CN81XX SoC<br>* Add documentation for CN81XX EVB SFF mainboard<br>* Add documentation for BDK<br>* Add documentation for BOOTROM and BOOTBLOCK behaviour<br>* Alphabetically sort vendors<br><br>Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>Reviewed-on: https://review.coreboot.org/27150<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: David Hendricks <david.hendricks@gmail.com><br>Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com><br>---<br>M Documentation/index.md<br>A Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg<br>A Documentation/mainboard/cavium/cn8100_sff_evb.md<br>M Documentation/mainboard/index.md<br>A Documentation/soc/cavium/bootflow.md<br>A Documentation/soc/cavium/cavium_bootflow.png<br>A Documentation/soc/cavium/cn81xx/index.md<br>A Documentation/soc/cavium/index.md<br>M Documentation/soc/index.md<br>A Documentation/vendorcode/cavium/bdk.md<br>A Documentation/vendorcode/cavium/index.md<br>A Documentation/vendorcode/index.md<br>12 files changed, 275 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/index.md b/Documentation/index.md</span><br><span>index 4ec4550..cf22dca 100644</span><br><span>--- a/Documentation/index.md</span><br><span>+++ b/Documentation/index.md</span><br><span>@@ -18,4 +18,5 @@</span><br><span> * [System on Chip-specific documentation](soc/index.md)</span><br><span> * [Mainboard-specific documentation](mainboard/index.md)</span><br><span> * [SuperIO-specific documentation](superio/index.md)</span><br><span style="color: hsl(120, 100%, 40%);">+* [Vendorcode-specific documentation](vendorcode/index.md)</span><br><span> * [Release notes for past releases](releases/index.md)</span><br><span>diff --git a/Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg b/Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg</span><br><span>new file mode 100644</span><br><span>index 0000000..0afe778</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg</span><br><span>Binary files differ</span><br><span>diff --git a/Documentation/mainboard/cavium/cn8100_sff_evb.md b/Documentation/mainboard/cavium/cn8100_sff_evb.md</span><br><span>new file mode 100644</span><br><span>index 0000000..b16a8ae</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/cavium/cn8100_sff_evb.md</span><br><span>@@ -0,0 +1,76 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# CN81xx Evaluation-board SFF</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Specs</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* 3 mini PCIe slots</span><br><span style="color: hsl(120, 100%, 40%);">+* 4 SATA ports</span><br><span style="color: hsl(120, 100%, 40%);">+* one USB3.0 A connector</span><br><span style="color: hsl(120, 100%, 40%);">+* 20Pin JTAG</span><br><span style="color: hsl(120, 100%, 40%);">+* 4 Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+* 2 SFP+ connectors</span><br><span style="color: hsl(120, 100%, 40%);">+* PCIe x4 slot</span><br><span style="color: hsl(120, 100%, 40%);">+* UART over USB</span><br><span style="color: hsl(120, 100%, 40%);">+* eMMC Flash or MicroSD card slot for on-board storage</span><br><span style="color: hsl(120, 100%, 40%);">+* 1 Slot with DDR-4 memory with ECC support</span><br><span style="color: hsl(120, 100%, 40%);">+* SPI flash</span><br><span style="color: hsl(120, 100%, 40%);">+* MMC and uSD-card</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Flashing coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+----------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Type | Value |</span><br><span style="color: hsl(120, 100%, 40%);">++=====================+================+</span><br><span style="color: hsl(120, 100%, 40%);">+| Socketed flash | no |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+----------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Model | Micron 25Q128A |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+----------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Size | 8 MiB |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+----------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| In circuit flashing | no |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+----------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Package | SOIC-8 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+----------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Write protection | No |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+----------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Dual BIOS feature | No |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+----------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Internal flashing | ? |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+----------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Notes about the hardware</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+1. Cavium connected *GPIO10* to a global reset line.</span><br><span style="color: hsl(120, 100%, 40%);">+ It's unclear which chips are connected, but at least the PHY and SATA chips</span><br><span style="color: hsl(120, 100%, 40%);">+ are connected.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+2. The 4 QLMs can be configured using DIP switches (SW1). That means only a</span><br><span style="color: hsl(120, 100%, 40%);">+ subset of of the available connectors is working at time.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+3. The boot source can be configure using DIP switches (SW1).</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+4. The core and system clock frequency can be configured using DIP switches</span><br><span style="color: hsl(120, 100%, 40%);">+ (SW3 / SW2).</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+5. The JTAG follows Cavium's own protocol. Support for it is missing in</span><br><span style="color: hsl(120, 100%, 40%);">+ OpenOCD. You have to use ARMs official hardware and software.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Technology</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++---------------+----------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| SoC | :doc:`../../soc/cavium/cn81xx/index` |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------+----------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CPU | Cavium ARMv8-Quadcore `CN81XX`_ |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------+----------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Picture</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+![][cn81xx_board]</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[cn81xx_board]: cavium_cn81xx_sff_evb.jpg</span><br><span>diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md</span><br><span>index 23e1ed2..198211d 100644</span><br><span>--- a/Documentation/mainboard/index.md</span><br><span>+++ b/Documentation/mainboard/index.md</span><br><span>@@ -2,10 +2,14 @@</span><br><span> </span><br><span> This section contains documentation about coreboot on specific mainboards.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-## SiFive</span><br><span style="color: hsl(120, 100%, 40%);">+## Cavium</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)</span><br><span style="color: hsl(120, 100%, 40%);">+- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)</span><br><span> </span><br><span> ## HP</span><br><span> </span><br><span> - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## SiFive</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)</span><br><span>diff --git a/Documentation/soc/cavium/bootflow.md b/Documentation/soc/cavium/bootflow.md</span><br><span>new file mode 100644</span><br><span>index 0000000..70bf865</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/soc/cavium/bootflow.md</span><br><span>@@ -0,0 +1,19 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# Cavium bootflow</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The on-chip **BOOTROM** first sets up the L2 cache and the SPI controller.</span><br><span style="color: hsl(120, 100%, 40%);">+It then reads **CSIB_NBL1FW** and **CLIB_NBL1FW** configuration data to get</span><br><span style="color: hsl(120, 100%, 40%);">+the position of the bootstage in flash. It then loads 192KiB from flash into</span><br><span style="color: hsl(120, 100%, 40%);">+L2 cache to a fixed address. The boot mode is called "Non-Secure-Boot" as</span><br><span style="color: hsl(120, 100%, 40%);">+the signature of the bootstage isn't verified.</span><br><span style="color: hsl(120, 100%, 40%);">+The **BOOTROM** can do AES decryption for obfuscation or verify the signature</span><br><span style="color: hsl(120, 100%, 40%);">+of the bootstage. Both features aren't used and won't be described any further.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* The typical position of bootstage in flash is at address **0x20000**.</span><br><span style="color: hsl(120, 100%, 40%);">+* The entry point in physical DRAM is at address **0x100000**.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Layout</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+![Bootflow of Cavium CN8xxx SoCs][cavium_bootflow]</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[cavium_bootflow]: cavium_bootflow.png</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/Documentation/soc/cavium/cavium_bootflow.png b/Documentation/soc/cavium/cavium_bootflow.png</span><br><span>new file mode 100644</span><br><span>index 0000000..1e90173</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/soc/cavium/cavium_bootflow.png</span><br><span>Binary files differ</span><br><span>diff --git a/Documentation/soc/cavium/cn81xx/index.md b/Documentation/soc/cavium/cn81xx/index.md</span><br><span>new file mode 100644</span><br><span>index 0000000..69fe710</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/soc/cavium/cn81xx/index.md</span><br><span>@@ -0,0 +1,119 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# Cavium CN81xx documentation</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Reference code</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">+The Cavium reference code is called `BDK`_ (board development kit) and is part</span><br><span style="color: hsl(120, 100%, 40%);">+of the `Octeon-TX-SDK`_. Parts of the `BDK`_ have been integrated into coreoboot.</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## SOC code</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The SOC folder contains functions for:</span><br><span style="color: hsl(120, 100%, 40%);">+* TWSI</span><br><span style="color: hsl(120, 100%, 40%);">+* UART</span><br><span style="color: hsl(120, 100%, 40%);">+* TIMER</span><br><span style="color: hsl(120, 100%, 40%);">+* SPI</span><br><span style="color: hsl(120, 100%, 40%);">+* MMU</span><br><span style="color: hsl(120, 100%, 40%);">+* DRAM</span><br><span style="color: hsl(120, 100%, 40%);">+* CLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+* GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+* Secondary CPUs</span><br><span style="color: hsl(120, 100%, 40%);">+* PCI</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+All other hardware is initilized by the BDK code, which is invoked from</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Notes about the hardware</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Cavium SoC do **not** have embedded SRAM. The **BOOTROM** setups the</span><br><span style="color: hsl(120, 100%, 40%);">+L2 cache and loads 192KiB of firmware starting from 0x20000 to a fixed</span><br><span style="color: hsl(120, 100%, 40%);">+location. It then jumps to the firmware.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">+For more details have a look at `Cavium CN8XXX Bootflow`_.</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## CAR setup</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+For Cache-as-RAM we only need to lock the cachelines which are used by bootblock</span><br><span style="color: hsl(120, 100%, 40%);">+or romstage until DRAM has been set up. At the end of romstage the cachelines</span><br><span style="color: hsl(120, 100%, 40%);">+are unlocked and the contents are flushed to DRAM.</span><br><span style="color: hsl(120, 100%, 40%);">+Locked cachelines are never evicted.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The CAR setup is done in '''bootblock_custom.S''' and thus doesn't use the common</span><br><span style="color: hsl(120, 100%, 40%);">+aarch64 '''bootblock.S''' code.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## DRAM setup</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">+The DRAM setup is done by the `BDK`_.</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## PCI setup</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The PCI setup is done using the MMCONF mechanism.</span><br><span style="color: hsl(120, 100%, 40%);">+Besides configuring device visibility (secure/unsecure) the MSI-X interrupts</span><br><span style="color: hsl(120, 100%, 40%);">+needs to be configured.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Devicetree patching</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The Linux devicetree needs to be patched, depending on the available hardware</span><br><span style="color: hsl(120, 100%, 40%);">+and their configuration. Some values depends on fuses, some on user selectable</span><br><span style="color: hsl(120, 100%, 40%);">+configuration.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The following SoC specific fixes are made:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+1. Fix SCLK</span><br><span style="color: hsl(120, 100%, 40%);">+2. Fix UUA refclock</span><br><span style="color: hsl(120, 100%, 40%);">+3. Remove unused PEM entries</span><br><span style="color: hsl(120, 100%, 40%);">+4. Remove unused QLM entries</span><br><span style="color: hsl(120, 100%, 40%);">+5. Set local MAC address</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## CN81xx quirks</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The CN81xx needs some quirks that are not documented or hidden in the code.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Violation of PCI spec</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**Problem:**</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* The PCI device 01:01.0 is disabled, but a multifunction device.</span><br><span style="color: hsl(120, 100%, 40%);">+* The PCI device 01:01.2 - 00:01.7 is enabled and can't be found by the coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI allocator.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**Solution:**</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The PCI Bus 0 and 1 are scanned manually in SOC's PCI code.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Crash accessing SLI memory</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**Problem:**</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The SLI memory region decodes to attached PCIe devices.</span><br><span style="color: hsl(120, 100%, 40%);">+Accessing the memory region results in 'Data Abort Exception' if the link of the</span><br><span style="color: hsl(120, 100%, 40%);">+PCIe device never had been enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**Solution:**</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Enable the PCIe link at least once. (You can disabling the link and the SLI</span><br><span style="color: hsl(120, 100%, 40%);">+memory reads as 0xffffffff.)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### RNG Data Abort Exception</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**Problem:**</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+'Data Abort Exception' on accessing the enabled RNG.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**Solution**:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Read the BDK_RNM_CTL_STATUS register at least once after writing it.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">+.. _Octeon-TX-SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK</span><br><span style="color: hsl(120, 100%, 40%);">+.. _Cavium CN8XXX Bootflow: ../bootflow.html</span><br><span style="color: hsl(120, 100%, 40%);">+.. _BDK: ../../../vendorcode/cavium/bdk.html</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span>diff --git a/Documentation/soc/cavium/index.md b/Documentation/soc/cavium/index.md</span><br><span>new file mode 100644</span><br><span>index 0000000..5ccb47f</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/soc/cavium/index.md</span><br><span>@@ -0,0 +1,8 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# Cavium SOC-specific documentation</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This section contains documentation about coreboot on specific Cavium SOCs.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Platforms</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [CN81xx series](cn81xx/index.md)</span><br><span style="color: hsl(120, 100%, 40%);">+- [CN8xxx bootflow](bootflow.md)</span><br><span>diff --git a/Documentation/soc/index.md b/Documentation/soc/index.md</span><br><span>index ca50dc8..04e2b2f 100644</span><br><span>--- a/Documentation/soc/index.md</span><br><span>+++ b/Documentation/soc/index.md</span><br><span>@@ -4,4 +4,5 @@</span><br><span> </span><br><span> ## Vendor</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+- [Cavium](cavium/index.md)</span><br><span> - [Intel](intel/index.md)</span><br><span>diff --git a/Documentation/vendorcode/cavium/bdk.md b/Documentation/vendorcode/cavium/bdk.md</span><br><span>new file mode 100644</span><br><span>index 0000000..5763ece</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/vendorcode/cavium/bdk.md</span><br><span>@@ -0,0 +1,30 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# Cavium's BDK</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## BDK</span><br><span style="color: hsl(120, 100%, 40%);">+A part of Cavium's BDK can be found in '''src/vendorcode/cavium/bdk'''.</span><br><span style="color: hsl(120, 100%, 40%);">+It does the **DRAM init** in romstage and the **PCIe**, **QLM**, **SLI**,</span><br><span style="color: hsl(120, 100%, 40%);">+**PHY**, **BGX**, **SATA** init in ramstage.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Devicetree</span><br><span style="color: hsl(120, 100%, 40%);">+The BDK does use it's own devicetree, as coreboot's devicetree isn't</span><br><span style="color: hsl(120, 100%, 40%);">+compatible. The devicetree stores key-value pairs (see **bdk-devicetree.h**</span><br><span style="color: hsl(120, 100%, 40%);">+for implementation details), where the key and the value are stored as strings.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The key-value pairs must be advertised in romstage and ramstage using the</span><br><span style="color: hsl(120, 100%, 40%);">+'''bdk_config_set_fdt()''' method.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The tool '''util/cavium/devicetree_convert.py''' can be used to convert a</span><br><span style="color: hsl(120, 100%, 40%);">+devicetree to a key-value array.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Modifications</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* The BDK has been modified to compile under coreboot's toolchain.</span><br><span style="color: hsl(120, 100%, 40%);">+* Removed FDT devicetree support.</span><br><span style="color: hsl(120, 100%, 40%);">+* Dropped files that aren't required for SoC bringup</span><br><span style="color: hsl(120, 100%, 40%);">+* Added Kconfig values for verbose console output</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Debugging</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+You can enable verbose console output in *menuconfig*:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Go to **Chipset**, **BDK** and enable one or multiple stages.</span><br><span>diff --git a/Documentation/vendorcode/cavium/index.md b/Documentation/vendorcode/cavium/index.md</span><br><span>new file mode 100644</span><br><span>index 0000000..e06e2ba</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/vendorcode/cavium/index.md</span><br><span>@@ -0,0 +1,8 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# Cavium vendorcode-specific documentation</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This section contains documentation about coreboot on Cavium specific</span><br><span style="color: hsl(120, 100%, 40%);">+vendorcode.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Sections</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [BDK](bdk.md)</span><br><span>diff --git a/Documentation/vendorcode/index.md b/Documentation/vendorcode/index.md</span><br><span>new file mode 100644</span><br><span>index 0000000..3374eaf</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/vendorcode/index.md</span><br><span>@@ -0,0 +1,7 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# Vendorcode-specific documentation</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This section contains documentation about coreboot on specific vendorcode.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Vendor</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [Cavium](cavium/index.md)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27150">change 27150</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27150"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
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<div style="display:none"> Gerrit-Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 </div>
<div style="display:none"> Gerrit-Change-Number: 27150 </div>
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<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>
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<div style="display:none"> Gerrit-CC: Arthur Heymans <arthur@aheymans.xyz> </div>