<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/27093">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
Arthur Heymans: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Documentation: Add SandyBridge NRI feature matrix<br><br>Change-Id: I69b014430802de132c8d9b6c8409bc762b995468<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>Reviewed-on: https://review.coreboot.org/27093<br>Reviewed-by: Martin Roth <martinroth@google.com><br>Reviewed-by: Arthur Heymans <arthur@aheymans.xyz><br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>---<br>M Documentation/northbridge/intel/sandybridge/index.md<br>A Documentation/northbridge/intel/sandybridge/nri_features.md<br>2 files changed, 90 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md</span><br><span>index 815abce..dcb090a 100644</span><br><span>--- a/Documentation/northbridge/intel/sandybridge/index.md</span><br><span>+++ b/Documentation/northbridge/intel/sandybridge/index.md</span><br><span>@@ -5,3 +5,4 @@</span><br><span> ## Topics</span><br><span> </span><br><span> - [Native Ram Initialization](nri.md)</span><br><span style="color: hsl(120, 100%, 40%);">+- [RAM initialization feature matrix](nri_features.md)</span><br><span>diff --git a/Documentation/northbridge/intel/sandybridge/nri_features.md b/Documentation/northbridge/intel/sandybridge/nri_features.md</span><br><span>new file mode 100644</span><br><span>index 0000000..6305e78</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/northbridge/intel/sandybridge/nri_features.md</span><br><span>@@ -0,0 +1,89 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# RAM initialization feature matrix</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Options</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+1. Native raminit</span><br><span style="color: hsl(120, 100%, 40%);">+ * Open Source</span><br><span style="color: hsl(120, 100%, 40%);">+ * Native Raminit is working for most frequencies on most boards.</span><br><span style="color: hsl(120, 100%, 40%);">+ * There might be errors to fix.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Position in romstage doesn't matter.</span><br><span style="color: hsl(120, 100%, 40%);">+2. mrc.bin raminit</span><br><span style="color: hsl(120, 100%, 40%);">+ * Closed Source (aka BLOB)</span><br><span style="color: hsl(120, 100%, 40%);">+ * No known errors.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Needs to be placed at fixed offset in romstage.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Native raminit implemented features</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Option | Supported | Implemented | Working | Description |</span><br><span style="color: hsl(120, 100%, 40%);">++===========================+======================+=============+=========+=====================+</span><br><span style="color: hsl(120, 100%, 40%);">+| **Supported channels** |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| single and dual channel | yes | yes | yes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Up to 4 slots | yes | yes | yes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Up to 4 ranks per channel | yes | yes | yes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| **Supported frequencies** |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DDR3-1066 (533MHz) | yes | yes | yes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DDR3-1600 (800MHz) | yes | yes | yes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DDR3-1866 (933MHz) | yes | yes | yes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DDR3-2133 (1066MHz) | yes | yes | yes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DDR3-1400 (700MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DDR3-1800 (900MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DDR3-2000 (1000MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DDR3-2200 (1100MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DDR3-2400 (1200MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| DDR3-1800 (900MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| **Supported CAS latencies** |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CL6 | yes | yes | ? | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CL7 | yes | yes | ? | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CL8 | yes | yes | ? | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CL9 | yes | yes | ? | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CL10 | yes | yes | yes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CL11 | yes | yes | yes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CL12 | yes | yes | ? | Since coreboot 4.6 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CL13 | yes | yes | yes | Since coreboot 4.6 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CL14 | yes | yes | ? | Since coreboot 4.6 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CL15 | yes | yes | ? | Since coreboot 4.6 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| **MRC cache (stored timings of last training)** |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| S3 | yes | yes | yes | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| normal boot | yes | yes | yes | reset on CRC16 diff |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| **XMP support** |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| XMP Profile 1 | yes | yes | yes | only 1.5 V profiles |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| XMP Profile 2 | yes | yes | no | not activated |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| **ECC support** |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| ECC | yes | no | | |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------------+----------------------+-------------+---------+---------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27093">change 27093</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I69b014430802de132c8d9b6c8409bc762b995468 </div>
<div style="display:none"> Gerrit-Change-Number: 27093 </div>
<div style="display:none"> Gerrit-PatchSet: 4 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>