<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27113">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Remove DRAM_DMA section.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=work fine on Kukui<br><br>Change-Id: I6ba0757adbf4f1f8d2688e5ab1a36007e4e0d0fd<br>Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com><br>---<br>M src/soc/mediatek/mt8183/include/soc/memlayout.ld<br>1 file changed, 1 insertion(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/27113/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld</span><br><span>index 541f21e..f44c74b 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld</span><br><span>@@ -25,11 +25,6 @@</span><br><span> #define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr)</span><br><span> #define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define DRAM_DMA(addr, size) \</span><br><span style="color: hsl(0, 100%, 40%);">-      REGION(dram_dma, addr, size, 4K) \</span><br><span style="color: hsl(0, 100%, 40%);">-      _ = ASSERT(size % 4K == 0, \</span><br><span style="color: hsl(0, 100%, 40%);">-            "DRAM DMA buffer should be multiple of smallest page size (4K)!");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> SECTIONS</span><br><span> {</span><br><span>        SRAM_START(0x00100000)</span><br><span>@@ -50,7 +45,6 @@</span><br><span>   SRAM_L2C_END(0x00280000)</span><br><span> </span><br><span>         DRAM_START(0x40000000)</span><br><span style="color: hsl(0, 100%, 40%);">-  DRAM_DMA(0x40000000, 1M)</span><br><span style="color: hsl(0, 100%, 40%);">-        POSTRAM_CBFS_CACHE(0x40100000, 1M)</span><br><span style="color: hsl(120, 100%, 40%);">+    POSTRAM_CBFS_CACHE(0x40000000, 2M)</span><br><span>   RAMSTAGE(0x40200000, 256K)</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27113">change 27113</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27113"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6ba0757adbf4f1f8d2688e5ab1a36007e4e0d0fd </div>
<div style="display:none"> Gerrit-Change-Number: 27113 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>