<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27103">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/cavium: Enable DRAM test<br><br>Enable fast or extended DRAM test based on devicetree setting.<br>The fast DRAM test takes less than a second, while the<br>extended runs about 1 minute.<br><br>Tested on Cavium Soc.<br><br>Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c<br>M src/soc/cavium/cn81xx/sdram.c<br>2 files changed, 37 insertions(+), 21 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/27103/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c b/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c</span><br><span>index 76eaeb2..551266a 100644</span><br><span>--- a/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c</span><br><span>+++ b/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c</span><br><span>@@ -5,6 +5,7 @@</span><br><span> #include <bdk-devicetree.h></span><br><span> </span><br><span> const struct bdk_devicetree_key_value devtree[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-TEST-BOOT", "1"},</span><br><span> {"DDR-CONFIG-DQX-CTL", "0x4"},</span><br><span> {"DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2", "0xc0c0303"},</span><br><span> {"DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1", "0x1030203"},</span><br><span>diff --git a/src/soc/cavium/cn81xx/sdram.c b/src/soc/cavium/cn81xx/sdram.c</span><br><span>index 850c929..f7529d9 100644</span><br><span>--- a/src/soc/cavium/cn81xx/sdram.c</span><br><span>+++ b/src/soc/cavium/cn81xx/sdram.c</span><br><span>@@ -53,30 +53,45 @@</span><br><span> </span><br><span> /* See if we should test this node's DRAM during boot */</span><br><span> int test_dram = bdk_config_get_int(BDK_CONFIG_DRAM_BOOT_TEST, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (test_dram) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Run the address test to make sure DRAM works */</span><br><span style="color: hsl(0, 100%, 40%);">- if (bdk_dram_test(13, 0, 0x10000000000ull, BDK_DRAM_TEST_NO_STATS | (1<<0))) {</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * FIXME(dhendrix): This should be handled by mainboard code since we</span><br><span style="color: hsl(0, 100%, 40%);">- * don't necessarily have a BMC to report to. Also, we need to figure out</span><br><span style="color: hsl(0, 100%, 40%);">- * if we need to keep going as to avoid getting into a boot loop.</span><br><span style="color: hsl(0, 100%, 40%);">- * */</span><br><span style="color: hsl(0, 100%, 40%);">- // bdk_boot_status(BDK_BOOT_STATUS_REQUEST_POWER_CYCLE);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "%s: Failed DRAM test.\n", __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (test_dram == 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const u8 tests[] = {13, 0, 1};</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t i = 0; i < ARRAY_SIZE(tests); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Run the address test to make sure DRAM works */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bdk_dram_test(tests[i], 4 * MiB,</span><br><span style="color: hsl(120, 100%, 40%);">+ sdram_size_mb() * MiB - 4 * MiB,</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_DRAM_TEST_NO_STATS |</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_DRAM_TEST_NODE0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_CRIT,</span><br><span style="color: hsl(120, 100%, 40%);">+ "%s: Failed DRAM test.\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ bdk_watchdog_poke();</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- bdk_watchdog_poke();</span><br><span style="color: hsl(0, 100%, 40%);">- /* Put other node core back in reset */</span><br><span style="color: hsl(0, 100%, 40%);">- if (0 != bdk_numa_master())</span><br><span style="color: hsl(0, 100%, 40%);">- BDK_CSR_WRITE(0, BDK_RST_PP_RESET, -1);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear DRAM */</span><br><span style="color: hsl(0, 100%, 40%);">- uint64_t skip = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- if (0 == bdk_numa_master())</span><br><span style="color: hsl(0, 100%, 40%);">- skip = bdk_dram_get_top_of_bdk();</span><br><span style="color: hsl(0, 100%, 40%);">- void *base = bdk_phys_to_ptr(bdk_numa_get_address(0, skip));</span><br><span style="color: hsl(0, 100%, 40%);">- bdk_zero_memory(base, ((uint64_t)mbytes << 20) - skip);</span><br><span style="color: hsl(0, 100%, 40%);">- bdk_watchdog_poke();</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Run the address test to make sure DRAM works */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bdk_dram_test(13, 4 * MiB,</span><br><span style="color: hsl(120, 100%, 40%);">+ sdram_size_mb() * MiB - 4 * MiB,</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_DRAM_TEST_NO_STATS |</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_DRAM_TEST_NODE0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_CRIT,</span><br><span style="color: hsl(120, 100%, 40%);">+ "%s: Failed DRAM test.\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ bdk_watchdog_poke();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Put other node core back in reset */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (0 != bdk_numa_master())</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_CSR_WRITE(0, BDK_RST_PP_RESET, -1);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear DRAM */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t skip = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (0 == bdk_numa_master())</span><br><span style="color: hsl(120, 100%, 40%);">+ skip = bdk_dram_get_top_of_bdk();</span><br><span style="color: hsl(120, 100%, 40%);">+ void *base = bdk_phys_to_ptr(bdk_numa_get_address(0, skip));</span><br><span style="color: hsl(120, 100%, 40%);">+ bdk_zero_memory(base, ((uint64_t)mbytes << 20) - skip);</span><br><span style="color: hsl(120, 100%, 40%);">+ bdk_watchdog_poke();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Unlock L2 now that DRAM works */</span><br><span> if (0 == bdk_numa_master()) {</span><br><span> uint64_t l2_size = bdk_l2c_get_cache_size_bytes(0);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27103">change 27103</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf </div>
<div style="display:none"> Gerrit-Change-Number: 27103 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>