<p>Seunghwan Kim has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27099">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy/variant/nautilus: Correct USB OC pin configuration<br><br>Due to schematic, we need to correct USB OC pin configuration.<br> - OC0 for Type-C Port 1<br> - OC1 for Type-C Port 0<br> - OC2 for Type-A Port<br> - OC3 to NC<br><br>BUG=NONE<br>BRANCH=poppy<br>TEST=emerge-nautilus coreboot<br><br>Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687<br>Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com><br>---<br>M src/mainboard/google/poppy/variants/nautilus/devicetree.cb<br>M src/mainboard/google/poppy/variants/nautilus/gpio.c<br>2 files changed, 10 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/27099/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb</span><br><span>index 39d7353..79bb5fb 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb</span><br><span>@@ -167,16 +167,16 @@</span><br><span>   # RP 1, Enable Latency Tolerance Reporting Mechanism</span><br><span>         register "PcieRpLtrEnable[0]" = "1"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"    # Type-C Port 1</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)"       # Type-A Port</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_LONG(OC1)"    # Type-C Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+       register "usb2_ports[1]" = "USB2_PORT_SHORT(OC2)"   # Type-A Port</span><br><span>        register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"       # Bluetooth</span><br><span style="color: hsl(0, 100%, 40%);">-     register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"    # Type-C Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+       register "usb2_ports[4]" = "USB2_PORT_LONG(OC0)"    # Type-C Port 2</span><br><span>      register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)"       # H1</span><br><span>         register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)"       # Camera</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-    register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"     # Type-A Port</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+       register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+       register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port</span><br><span>        register "usb3_ports[3]" = "USB3_PORT_EMPTY"                # Empty</span><br><span> </span><br><span>  # Intel Common SoC Config</span><br><span>diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c</span><br><span>index 839f425..b4db7ee 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nautilus/gpio.c</span><br><span>+++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c</span><br><span>@@ -231,10 +231,10 @@</span><br><span>   PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),</span><br><span>         /* E10 : USB2_OC1# ==> USB3_C0_OC0_L */</span><br><span>   PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-   /* E11 : USB2_OC2# ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_E11),</span><br><span style="color: hsl(0, 100%, 40%);">-    /* E12 : USB2_OC3# ==> USB2_OC3_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E11 : USB2_OC2# ==> USB2_P2_FAULT# */</span><br><span style="color: hsl(120, 100%, 40%);">+   PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E12 : USB2_OC3# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+       PAD_CFG_NC(GPP_E12),</span><br><span>         /* E13 : DDPB_HPD0 ==> KBC3_USB_C0_DP_HPD */</span><br><span>      PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),</span><br><span>      /* E14 : DDPC_HPD1 ==> KBC3_USB_C1_DP_HPD */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27099">change 27099</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27099"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687 </div>
<div style="display:none"> Gerrit-Change-Number: 27099 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Seunghwan Kim <sh_.kim@samsung.com> </div>