<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27110">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/southbridge.c: Log failed S3 resume<br><br>Newly defined structure soc_power_reg includes information on last sleep<br>type (S3/S5) extracted from power management control register. If the last<br>sleep type was S3, but code is about to load an OS (normal boot), we have<br>a situation in which S3 resume failed and was converted into a regular boot.<br>We need to log this event.<br><br>BUG=b:110225041<br>TEST=The fact that wake_from variable is working was proved in parent<br>commit. So add code to fake S3 resume in a normal boot. Build and boot<br>grunt, verify failed S3 resume was logged. Remove fake S3 resume.<br><br>Change-Id: I77e13ff30a0ca0e9b21fca47c9b60400129365a7<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/include/elog.h<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>3 files changed, 20 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/27110/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/include/elog.h b/src/include/elog.h</span><br><span>index 0776c36..03ec9a7 100644</span><br><span>--- a/src/include/elog.h</span><br><span>+++ b/src/include/elog.h</span><br><span>@@ -219,6 +219,11 @@</span><br><span> #define ELOG_TYPE_S0IX_ENTER 0xaf</span><br><span> #define ELOG_TYPE_S0IX_EXIT 0xb0</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Detected errors */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ELOG_TYPE_DETECTED_ERROR 0xb1</span><br><span style="color: hsl(120, 100%, 40%);">+#define ELOG_ERROR_S3_RESUME 0x00 /* failed resume, normal boot */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ELOG_ERROR_SECURITY 0x01 /* ex: failed TPM */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #if IS_ENABLED(CONFIG_ELOG)</span><br><span> /* Eventlog backing storage must be initialized before calling elog_init(). */</span><br><span> extern int elog_init(void);</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 40cf621..ac5033d 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -416,6 +416,7 @@</span><br><span> void xhci_pm_write32(uint8_t reg, uint32_t value);</span><br><span> uint32_t xhci_pm_read32(uint8_t reg);</span><br><span> void bootblock_fch_early_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void sb_log_error(uint8_t error);</span><br><span> /**</span><br><span> * @brief Save the UMA bize returned by AGESA</span><br><span> *</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 0f69e5b..651809c 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -514,6 +514,14 @@</span><br><span> pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void sb_log_error(uint8_t error)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_ELOG))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ elog_add_event_byte(ELOG_TYPE_DETECTED_ERROR, error);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void sb_lpc_early_setup(void)</span><br><span> {</span><br><span> uint32_t dword;</span><br><span>@@ -748,8 +756,14 @@</span><br><span> </span><br><span> void southbridge_final(void *chip_info)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct soc_power_reg *sws;</span><br><span> uint8_t restored_power = PM_S5_AT_POWER_RECOVERY;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ sws = cbmem_find(CBMEM_ID_POWER_STATE);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sws != NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sws->wake_from == 3)</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_log_error(ELOG_ERROR_S3_RESUME);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) {</span><br><span> agesawrapper_fchecfancontrolservice();</span><br><span> if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE))</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27110">change 27110</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I77e13ff30a0ca0e9b21fca47c9b60400129365a7 </div>
<div style="display:none"> Gerrit-Change-Number: 27110 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>