<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27087">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Documentation/Intel: Add common code design document<br><br>Add common code design document support Intel SoCs such as Skylake,<br>Cannonlake and Apollolake onwards.<br><br>Documented items:<br>*Introduction<br>*Design Principle<br>*Common code development and status<br>*Common code structure<br>*Benifits<br><br>Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>A Documentation/Intel/code_development_model/Code_development_model.md<br>A Documentation/Intel/code_development_model/coreboot_common_code_design.png<br>2 files changed, 93 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/27087/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/Intel/code_development_model/Code_development_model.md b/Documentation/Intel/code_development_model/Code_development_model.md</span><br><span>new file mode 100644</span><br><span>index 0000000..9e03404</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/Intel/code_development_model/Code_development_model.md</span><br><span>@@ -0,0 +1,93 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# Intel common code development strategy</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Introduction</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This document captures the development strategy for Intel SOC code development</span><br><span style="color: hsl(120, 100%, 40%);">+of coreboot. As Intel keeps advancing hardware development and as new generation</span><br><span style="color: hsl(120, 100%, 40%);">+SoC is developed, we also need to add support for these SOCs into coreboot.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+We add this support inside soc/intel/<soc name> folder. This folder contains all</span><br><span style="color: hsl(120, 100%, 40%);">+the files which are related to particular SoC.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+There might be still common code lying across some SoCs but this document</span><br><span style="color: hsl(120, 100%, 40%);">+captures our efforts on putting maximum code as a common code across all the</span><br><span style="color: hsl(120, 100%, 40%);">+SoCs and what can't be put into common code due to vulnerability to change in</span><br><span style="color: hsl(120, 100%, 40%);">+future.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Design principal</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Any Intel coreboot projects can be split into 3 parts:</span><br><span style="color: hsl(120, 100%, 40%);">+1. SoC = It contains all the IP/component initialization code</span><br><span style="color: hsl(120, 100%, 40%);">+2. Mainboard = OxM boards, build based on underlying SoC support</span><br><span style="color: hsl(120, 100%, 40%);">+3. FSP = Intel firmware support package to abstract all restricted SoC registers</span><br><span style="color: hsl(120, 100%, 40%);">+from open source world.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Historically, we used to copy "X-1" generation SoC code into "X" new SoC while</span><br><span style="color: hsl(120, 100%, 40%);">+adding support for new SoC at open source. This results in having same</span><br><span style="color: hsl(120, 100%, 40%);">+initialization code in both projects. This method increases redundant code</span><br><span style="color: hsl(120, 100%, 40%);">+across multiple SoCs and also it increases overhead for reviewers and</span><br><span style="color: hsl(120, 100%, 40%);">+maintainers also.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+To solve this issue, we started following converged IP model. Intel Silicon team</span><br><span style="color: hsl(120, 100%, 40%);">+uses same IP/controller across various Intel SoCs. For example, LPSS based UART</span><br><span style="color: hsl(120, 100%, 40%);">+controller is same across all SoC products. Thus "converged IP model" was</span><br><span style="color: hsl(120, 100%, 40%);">+propsed as firmware development model to create common IP library across</span><br><span style="color: hsl(120, 100%, 40%);">+multiple SoC products and creating BIOS/firmware for future SoC will be much</span><br><span style="color: hsl(120, 100%, 40%);">+simpler by just using those APIs based on certain configurations.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Common Code Development and Status</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Intel's proposed "converged IP model" is also called as common code phase 1.0,</span><br><span style="color: hsl(120, 100%, 40%);">+and it has reduced number of lines in single SoC folder by over 50%.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+We continue to analyze code which can still be moved to common and try to reduce</span><br><span style="color: hsl(120, 100%, 40%);">+footprint of the code lying in each SoC folder. With current Intel SoC</span><br><span style="color: hsl(120, 100%, 40%);">+development model, PCH is emerged as a separate component for big core SoCs.</span><br><span style="color: hsl(120, 100%, 40%);">+Intel hardware design started following model where same PCH is used across</span><br><span style="color: hsl(120, 100%, 40%);">+multiple SoCs, which gives us an opportunity to make code more common across</span><br><span style="color: hsl(120, 100%, 40%);">+SoCs which uses same PCH. As part of this idea, common code phase 1.1 has</span><br><span style="color: hsl(120, 100%, 40%);">+emerged and we'll try to create PCH binding for SoCs and thus further reducing</span><br><span style="color: hsl(120, 100%, 40%);">+footprint of SoC code.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Common code phase 1.1 will make code more modular for big core SoCs but there</span><br><span style="color: hsl(120, 100%, 40%);">+is still some scope to make code flow common across small core and big core</span><br><span style="color: hsl(120, 100%, 40%);">+SoCs. We will take it up as a part of common code phase 2.0 and make code flow</span><br><span style="color: hsl(120, 100%, 40%);">+common across small core and big core SoCs which will help us to reduce the</span><br><span style="color: hsl(120, 100%, 40%);">+footprint of code as well as have a unified code flow for all Intel SoCs.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Here's a table which summarizes common code phase and status:</span><br><span style="color: hsl(120, 100%, 40%);">+|-----------------------------------------------------------------------------|</span><br><span style="color: hsl(120, 100%, 40%);">+| Common code | summary | status |</span><br><span style="color: hsl(120, 100%, 40%);">+| phase | | |</span><br><span style="color: hsl(120, 100%, 40%);">+|-----------------------------------------------------------------------------|</span><br><span style="color: hsl(120, 100%, 40%);">+| 1.0 |follow "converged IP model" as described | Patches in |</span><br><span style="color: hsl(120, 100%, 40%);">+| |above and create common IP code which can be | Review |</span><br><span style="color: hsl(120, 100%, 40%);">+| |used across multiple SoCs | |</span><br><span style="color: hsl(120, 100%, 40%);">+|-----------------------------------------------------------------------------|</span><br><span style="color: hsl(120, 100%, 40%);">+| 1.1 |Create PCH binding for big core SoCs. SoCs |In development|</span><br><span style="color: hsl(120, 100%, 40%);">+| |having same PCH can use common code. |Base patch |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |merged |</span><br><span style="color: hsl(120, 100%, 40%);">+|-----------------------------------------------------------------------------|</span><br><span style="color: hsl(120, 100%, 40%);">+| 2.0 |Use common stage files (bootblock, romstage) |In development|</span><br><span style="color: hsl(120, 100%, 40%);">+| |across small core and big core SoCs. This | |</span><br><span style="color: hsl(120, 100%, 40%);">+| |will unify flow for all Intel SoCs. | |</span><br><span style="color: hsl(120, 100%, 40%);">+|-----------------------------------------------------------------------------|</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Common code structure</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Code design after common code in coreboot will look like as follow:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+![alt text][coreboot_common_code_design]</span><br><span style="color: hsl(120, 100%, 40%);">+[coreboot_common_code_design]: coreboot_common_code_design.png "coreboot common code structure"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+There will be still some files left in each SOC folder and we may copy it across</span><br><span style="color: hsl(120, 100%, 40%);">+SOC as a base but these files are vulnerable to change as development continues.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Benefits</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+1. coreboot will have less redundant code which is spread across multiple SOC</span><br><span style="color: hsl(120, 100%, 40%);">+as of now.</span><br><span style="color: hsl(120, 100%, 40%);">+2. Design will be easy to understand by community since code flow will be same</span><br><span style="color: hsl(120, 100%, 40%);">+for all the SoCs.</span><br><span style="color: hsl(120, 100%, 40%);">+3. Since we are aligning software code design with hardware philosophy, it'll</span><br><span style="color: hsl(120, 100%, 40%);">+be easier to map why each change was done in code/SOC.</span><br><span>diff --git a/Documentation/Intel/code_development_model/coreboot_common_code_design.png b/Documentation/Intel/code_development_model/coreboot_common_code_design.png</span><br><span>new file mode 100644</span><br><span>index 0000000..b5370ef</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/Intel/code_development_model/coreboot_common_code_design.png</span><br><span>Binary files differ</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27087">change 27087</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de </div>
<div style="display:none"> Gerrit-Change-Number: 27087 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>