<p>Bora Guvendik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27097">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: unify definition for spi base address<br><br>Use SPI_BASE_ADDRESS instead of PRERAM_SPI_BASE_ADDRESS like<br>big core in order make common code implementation straightforward.<br><br>Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6<br>Signed-off-by: Bora Guvendik <bora.guvendik@intel.com><br>---<br>M src/soc/intel/apollolake/bootblock/bootblock.c<br>M src/soc/intel/apollolake/include/soc/iomap.h<br>2 files changed, 2 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27097/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>index 81843a4..09ea91e 100644</span><br><span>--- a/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>+++ b/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>@@ -106,7 +106,7 @@</span><br><span> </span><br><span>  enable_pm_timer_emulation();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-        fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_early_init(SPI_BASE_ADDRESS);</span><br><span> </span><br><span>   fast_spi_cache_bios_region();</span><br><span> </span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h</span><br><span>index 9a2500c..479882f 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/iomap.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/iomap.h</span><br><span>@@ -47,7 +47,7 @@</span><br><span> #define HECI1_BASE_ADDRESS                0xfed1a000</span><br><span> </span><br><span> /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRERAM_SPI_BASE_ADDRESS           0xfe010000</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_BASE_ADDRESS            0xfe010000</span><br><span> #define EARLY_GSPI_BASE_ADDRESS           0xfe011000</span><br><span> </span><br><span> /* Temporary BAR for early I2C bus access */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27097">change 27097</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27097"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6 </div>
<div style="display:none"> Gerrit-Change-Number: 27097 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Bora Guvendik <bora.guvendik@intel.com> </div>