<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27038">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"<br><br>In the end it does not look like RCBA register offsets are fully<br>compatible over southbridges. So instead of trying to make all code<br>using RCBA access use common header, provide RCBA to common<br>southbridge code.<br><br>This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4.<br><br>Is squashed with revert of "sb/intel/common: Fix conflicting OIC<br>register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f.<br><br>Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/model_2065x/bootblock.c<br>M src/cpu/intel/model_206ax/bootblock.c<br>M src/mainboard/apple/macbookair4_2/early_southbridge.c<br>M src/mainboard/apple/macbookair4_2/mainboard.c<br>M src/mainboard/compulab/intense_pc/romstage.c<br>M src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c<br>M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c<br>M src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c<br>M src/mainboard/gigabyte/ga-b75m-d3v/romstage.c<br>M src/mainboard/google/butterfly/romstage.c<br>M src/mainboard/google/link/romstage.c<br>M src/mainboard/google/parrot/romstage.c<br>M src/mainboard/google/stout/romstage.c<br>M src/mainboard/hp/revolve_810_g1/romstage.c<br>M src/mainboard/intel/dcp847ske/early_southbridge.c<br>M src/mainboard/intel/emeraldlake2/romstage.c<br>M src/mainboard/kontron/ktqm77/romstage.c<br>M src/mainboard/lenovo/l520/romstage.c<br>M src/mainboard/lenovo/s230u/romstage.c<br>M src/mainboard/lenovo/t420/romstage.c<br>M src/mainboard/lenovo/t420s/romstage.c<br>M src/mainboard/lenovo/t430s/romstage.c<br>M src/mainboard/lenovo/t520/romstage.c<br>M src/mainboard/lenovo/t530/romstage.c<br>M src/mainboard/lenovo/x201/mainboard.c<br>M src/mainboard/lenovo/x201/romstage.c<br>M src/mainboard/lenovo/x220/romstage.c<br>M src/mainboard/lenovo/x230/romstage.c<br>M src/mainboard/packardbell/ms2290/romstage.c<br>M src/mainboard/roda/rv11/romstage.c<br>M src/mainboard/roda/rv11/variants/rv11/romstage.c<br>M src/mainboard/samsung/lumpy/romstage.c<br>M src/mainboard/samsung/stumpy/romstage.c<br>M src/mainboard/sapphire/pureplatinumh61/mainboard.c<br>M src/mainboard/sapphire/pureplatinumh61/romstage.c<br>M src/northbridge/intel/nehalem/early_init.c<br>M src/northbridge/intel/nehalem/nehalem.h<br>M src/northbridge/intel/nehalem/raminit.c<br>M src/northbridge/intel/sandybridge/early_init.c<br>M src/northbridge/intel/sandybridge/sandybridge.h<br>M src/southbridge/intel/bd82x6x/azalia.c<br>M src/southbridge/intel/bd82x6x/bootblock.c<br>M src/southbridge/intel/bd82x6x/early_pch.c<br>M src/southbridge/intel/bd82x6x/early_rcba.c<br>M src/southbridge/intel/bd82x6x/early_spi.c<br>M src/southbridge/intel/bd82x6x/early_thermal.c<br>M src/southbridge/intel/bd82x6x/finalize.c<br>M src/southbridge/intel/bd82x6x/lpc.c<br>M src/southbridge/intel/bd82x6x/me.c<br>M src/southbridge/intel/bd82x6x/me_8.x.c<br>M src/southbridge/intel/bd82x6x/pch.c<br>M src/southbridge/intel/bd82x6x/pch.h<br>M src/southbridge/intel/bd82x6x/pcie.c<br>M src/southbridge/intel/bd82x6x/smihandler.c<br>M src/southbridge/intel/bd82x6x/usb_ehci.c<br>D src/southbridge/intel/common/rcba.h<br>M src/southbridge/intel/common/rcba_pirq.c<br>A src/southbridge/intel/common/rcba_pirq.h<br>M src/southbridge/intel/ibexpeak/azalia.c<br>M src/southbridge/intel/ibexpeak/lpc.c<br>M src/southbridge/intel/ibexpeak/me.c<br>M src/southbridge/intel/ibexpeak/pch.h<br>M src/southbridge/intel/ibexpeak/smihandler.c<br>M src/southbridge/intel/ibexpeak/usb_ehci.c<br>64 files changed, 363 insertions(+), 294 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/27038/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c</span><br><span>index edc2996..ed528d1 100644</span><br><span>--- a/src/cpu/intel/model_2065x/bootblock.c</span><br><span>+++ b/src/cpu/intel/model_2065x/bootblock.c</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #include <cpu/intel/microcode/microcode.c></span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK)</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/ibexpeak/pch.h></span><br><span> #include "model_2065x.h"</span><br><span> #else</span><br><span>diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c</span><br><span>index 90215a4..670b097 100644</span><br><span>--- a/src/cpu/intel/model_206ax/bootblock.c</span><br><span>+++ b/src/cpu/intel/model_206ax/bootblock.c</span><br><span>@@ -28,7 +28,6 @@</span><br><span> IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)</span><br><span> /* Needed for RCBA access to set Soft Reset Data register */</span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #else</span><br><span> #error "CPU must be paired with Intel BD82X6X or C216 southbridge"</span><br><span> #endif</span><br><span>diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c</span><br><span>index 25ddb98..b9cfa20 100644</span><br><span>--- a/src/mainboard/apple/macbookair4_2/early_southbridge.c</span><br><span>+++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c</span><br><span>@@ -25,7 +25,6 @@</span><br><span> #include "northbridge/intel/sandybridge/sandybridge.h"</span><br><span> #include "northbridge/intel/sandybridge/raminit_native.h"</span><br><span> #include "southbridge/intel/bd82x6x/pch.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span> #include <cpu/x86/msr.h></span><br><span>diff --git a/src/mainboard/apple/macbookair4_2/mainboard.c b/src/mainboard/apple/macbookair4_2/mainboard.c</span><br><span>index cd0ab81..3606e26 100644</span><br><span>--- a/src/mainboard/apple/macbookair4_2/mainboard.c</span><br><span>+++ b/src/mainboard/apple/macbookair4_2/mainboard.c</span><br><span>@@ -13,7 +13,6 @@</span><br><span> </span><br><span> #include <device/device.h></span><br><span> #include <drivers/intel/gma/int15.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <ec/acpi/ec.h></span><br><span> #include <console/console.h></span><br><span>diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c</span><br><span>index 00a8d1f..6949246 100644</span><br><span>--- a/src/mainboard/compulab/intense_pc/romstage.c</span><br><span>+++ b/src/mainboard/compulab/intense_pc/romstage.c</span><br><span>@@ -18,7 +18,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include "northbridge/intel/sandybridge/raminit_native.h"</span><br><span> #include <superio/smsc/sio1007/chip.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #define SIO_PORT 0x164e</span><br><span> </span><br><span>diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c</span><br><span>index 7bc353c..90131ff 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include <arch/interrupt.h></span><br><span> #include <boot/coreboot_tables.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <smbios.h></span><br><span> #include <device/pci.h></span><br><span>diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c</span><br><span>index 92bef28..5a2c935 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c</span><br><span>@@ -28,7 +28,6 @@</span><br><span> #include <superio/ite/common/ite.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c</span><br><span>index 7bc353c..90131ff 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include <arch/interrupt.h></span><br><span> #include <boot/coreboot_tables.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <smbios.h></span><br><span> #include <device/pci.h></span><br><span>diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c</span><br><span>index 283ad46..a389e68 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c</span><br><span>@@ -28,7 +28,6 @@</span><br><span> #include <superio/ite/common/ite.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c</span><br><span>index ebcba84..3ef4659 100644</span><br><span>--- a/src/mainboard/google/butterfly/romstage.c</span><br><span>+++ b/src/mainboard/google/butterfly/romstage.c</span><br><span>@@ -29,7 +29,6 @@</span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>@@ -96,9 +95,9 @@</span><br><span> DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);</span><br><span> </span><br><span> /* Enable IOAPIC (generic) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA16(EOIC) = 0x0100;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(OIC) = 0x0100;</span><br><span> /* PCH BWG says to read back the IOAPIC enable register */</span><br><span style="color: hsl(0, 100%, 40%);">- (void) RCBA16(EOIC);</span><br><span style="color: hsl(120, 100%, 40%);">+ (void) RCBA16(OIC);</span><br><span> </span><br><span> /* Disable unused devices (board specific) */</span><br><span> reg32 = RCBA32(FD);</span><br><span>diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c</span><br><span>index cc2ef22..d9f00f4 100644</span><br><span>--- a/src/mainboard/google/link/romstage.c</span><br><span>+++ b/src/mainboard/google/link/romstage.c</span><br><span>@@ -30,7 +30,6 @@</span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include "ec/google/chromeec/ec.h"</span><br><span> #include <arch/cpu.h></span><br><span>@@ -104,9 +103,9 @@</span><br><span> DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);</span><br><span> </span><br><span> /* Enable IOAPIC (generic) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA16(EOIC) = 0x0100;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(OIC) = 0x0100;</span><br><span> /* PCH BWG says to read back the IOAPIC enable register */</span><br><span style="color: hsl(0, 100%, 40%);">- (void) RCBA16(EOIC);</span><br><span style="color: hsl(120, 100%, 40%);">+ (void) RCBA16(OIC);</span><br><span> }</span><br><span> </span><br><span> static uint8_t *locate_spd(void)</span><br><span>diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c</span><br><span>index 30fa7c2..6163c35 100644</span><br><span>--- a/src/mainboard/google/parrot/romstage.c</span><br><span>+++ b/src/mainboard/google/parrot/romstage.c</span><br><span>@@ -29,7 +29,6 @@</span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>@@ -95,9 +94,9 @@</span><br><span> DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);</span><br><span> </span><br><span> /* Enable IOAPIC (generic) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA16(EOIC) = 0x0100;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(OIC) = 0x0100;</span><br><span> /* PCH BWG says to read back the IOAPIC enable register */</span><br><span style="color: hsl(0, 100%, 40%);">- (void) RCBA16(EOIC);</span><br><span style="color: hsl(120, 100%, 40%);">+ (void) RCBA16(OIC);</span><br><span> </span><br><span> /* Disable unused devices (board specific) */</span><br><span> reg32 = RCBA32(FD);</span><br><span>diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c</span><br><span>index 9ad03f7..36ebcf7 100644</span><br><span>--- a/src/mainboard/google/stout/romstage.c</span><br><span>+++ b/src/mainboard/google/stout/romstage.c</span><br><span>@@ -29,7 +29,6 @@</span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>@@ -101,9 +100,9 @@</span><br><span> DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);</span><br><span> </span><br><span> /* Enable IOAPIC (generic) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA16(EOIC) = 0x0100;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(OIC) = 0x0100;</span><br><span> /* PCH BWG says to read back the IOAPIC enable register */</span><br><span style="color: hsl(0, 100%, 40%);">- (void) RCBA16(EOIC);</span><br><span style="color: hsl(120, 100%, 40%);">+ (void) RCBA16(OIC);</span><br><span> </span><br><span> /* Disable unused devices (board specific) */</span><br><span> reg32 = RCBA32(FD);</span><br><span>diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c</span><br><span>index 1eea89d..c70660a 100644</span><br><span>--- a/src/mainboard/hp/revolve_810_g1/romstage.c</span><br><span>+++ b/src/mainboard/hp/revolve_810_g1/romstage.c</span><br><span>@@ -21,7 +21,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <ec/hp/kbc1126/ec.h></span><br><span> </span><br><span>diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c</span><br><span>index 873718f..f334157 100644</span><br><span>--- a/src/mainboard/intel/dcp847ske/early_southbridge.c</span><br><span>+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c</span><br><span>@@ -23,7 +23,7 @@</span><br><span> #include <arch/acpi.h></span><br><span> #include <console/console.h></span><br><span> #include "northbridge/intel/sandybridge/raminit_native.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #include "superio.h"</span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c</span><br><span>index d23541f..cdc0874 100644</span><br><span>--- a/src/mainboard/intel/emeraldlake2/romstage.c</span><br><span>+++ b/src/mainboard/intel/emeraldlake2/romstage.c</span><br><span>@@ -31,7 +31,6 @@</span><br><span> #include <northbridge/intel/sandybridge/raminit.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span> #include <cpu/x86/msr.h></span><br><span>diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c</span><br><span>index bff4991..2a674a5 100644</span><br><span>--- a/src/mainboard/kontron/ktqm77/romstage.c</span><br><span>+++ b/src/mainboard/kontron/ktqm77/romstage.c</span><br><span>@@ -29,7 +29,6 @@</span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c</span><br><span>index de4e9f3..0f6ffed 100644</span><br><span>--- a/src/mainboard/lenovo/l520/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/l520/romstage.c</span><br><span>@@ -20,7 +20,6 @@</span><br><span> #include <device/pnp_def.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c</span><br><span>index 83664f4..b83eeae 100644</span><br><span>--- a/src/mainboard/lenovo/s230u/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/s230u/romstage.c</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #include <console/console.h></span><br><span> #include "northbridge/intel/sandybridge/sandybridge.h"</span><br><span> #include "northbridge/intel/sandybridge/raminit_native.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "southbridge/intel/bd82x6x/pch.h"</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c</span><br><span>index bac7288..36e83a3 100644</span><br><span>--- a/src/mainboard/lenovo/t420/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t420/romstage.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span>diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c</span><br><span>index 025a0fd..55011cf2 100644</span><br><span>--- a/src/mainboard/lenovo/t420s/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t420s/romstage.c</span><br><span>@@ -19,7 +19,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span>diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c</span><br><span>index 0e732ee..3f6d9f2 100644</span><br><span>--- a/src/mainboard/lenovo/t430s/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t430s/romstage.c</span><br><span>@@ -20,7 +20,6 @@</span><br><span> #include <device/pci_def.h></span><br><span> #include <console/console.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> </span><br><span> void pch_enable_lpc(void)</span><br><span>diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c</span><br><span>index 638e7ca..d752840 100644</span><br><span>--- a/src/mainboard/lenovo/t520/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t520/romstage.c</span><br><span>@@ -30,7 +30,6 @@</span><br><span> #include <console/console.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c</span><br><span>index 7470acc..ba7a229 100644</span><br><span>--- a/src/mainboard/lenovo/t530/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t530/romstage.c</span><br><span>@@ -21,7 +21,7 @@</span><br><span> #include <device/pci_def.h></span><br><span> #include <console/console.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h></span><br><span> #include <device/device.h></span><br><span>diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c</span><br><span>index 59add68..5d0deea 100644</span><br><span>--- a/src/mainboard/lenovo/x201/mainboard.c</span><br><span>+++ b/src/mainboard/lenovo/x201/mainboard.c</span><br><span>@@ -21,7 +21,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include <ec/acpi/ec.h></span><br><span> #include <northbridge/intel/nehalem/nehalem.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> </span><br><span> #include <pc80/mc146818rtc.h></span><br><span>diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c</span><br><span>index 1169a6ca..d93cb8c 100644</span><br><span>--- a/src/mainboard/lenovo/x201/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x201/romstage.c</span><br><span>@@ -39,7 +39,6 @@</span><br><span> </span><br><span> #include "dock.h"</span><br><span> #include "arch/early_variables.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/ibexpeak/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <northbridge/intel/nehalem/nehalem.h></span><br><span>diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c</span><br><span>index e38dfe7..96e0284 100644</span><br><span>--- a/src/mainboard/lenovo/x220/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x220/romstage.c</span><br><span>@@ -29,7 +29,6 @@</span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c</span><br><span>index 7801d57..1a7decc 100644</span><br><span>--- a/src/mainboard/lenovo/x230/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x230/romstage.c</span><br><span>@@ -30,7 +30,6 @@</span><br><span> #include <console/console.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c</span><br><span>index a52f153..3538647 100644</span><br><span>--- a/src/mainboard/packardbell/ms2290/romstage.c</span><br><span>+++ b/src/mainboard/packardbell/ms2290/romstage.c</span><br><span>@@ -37,7 +37,6 @@</span><br><span> #include <cbmem.h></span><br><span> </span><br><span> #include "arch/early_variables.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/ibexpeak/pch.h></span><br><span> #include <northbridge/intel/nehalem/nehalem.h></span><br><span> </span><br><span>diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/romstage.c</span><br><span>index 6a3a56e..b36725c 100644</span><br><span>--- a/src/mainboard/roda/rv11/romstage.c</span><br><span>+++ b/src/mainboard/roda/rv11/romstage.c</span><br><span>@@ -14,7 +14,6 @@</span><br><span> */</span><br><span> </span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> </span><br><span> void mainboard_rcba_config(void)</span><br><span>diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c</span><br><span>index 549167b..c7de994 100644</span><br><span>--- a/src/mainboard/roda/rv11/variants/rv11/romstage.c</span><br><span>+++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c</span><br><span>@@ -18,7 +18,6 @@</span><br><span> #include <northbridge/intel/sandybridge/raminit.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> </span><br><span> void pch_enable_lpc(void)</span><br><span>diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c</span><br><span>index 912d2c3..cea206a 100644</span><br><span>--- a/src/mainboard/samsung/lumpy/romstage.c</span><br><span>+++ b/src/mainboard/samsung/lumpy/romstage.c</span><br><span>@@ -32,7 +32,6 @@</span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>@@ -103,9 +102,9 @@</span><br><span> DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);</span><br><span> </span><br><span> /* Enable IOAPIC (generic) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA16(EOIC) = 0x0100;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(OIC) = 0x0100;</span><br><span> /* PCH BWG says to read back the IOAPIC enable register */</span><br><span style="color: hsl(0, 100%, 40%);">- (void) RCBA16(EOIC);</span><br><span style="color: hsl(120, 100%, 40%);">+ (void) RCBA16(OIC);</span><br><span> }</span><br><span> </span><br><span> static const uint8_t *locate_spd(void)</span><br><span>diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c</span><br><span>index 9f1e3f6..f502cc3 100644</span><br><span>--- a/src/mainboard/samsung/stumpy/romstage.c</span><br><span>+++ b/src/mainboard/samsung/stumpy/romstage.c</span><br><span>@@ -32,7 +32,6 @@</span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>@@ -112,9 +111,9 @@</span><br><span> DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);</span><br><span> </span><br><span> /* Enable IOAPIC (generic) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA16(EOIC) = 0x0100;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(OIC) = 0x0100;</span><br><span> /* PCH BWG says to read back the IOAPIC enable register */</span><br><span style="color: hsl(0, 100%, 40%);">- (void) RCBA16(EOIC);</span><br><span style="color: hsl(120, 100%, 40%);">+ (void) RCBA16(OIC);</span><br><span> }</span><br><span> </span><br><span> static void setup_sio_gpios(void)</span><br><span>diff --git a/src/mainboard/sapphire/pureplatinumh61/mainboard.c b/src/mainboard/sapphire/pureplatinumh61/mainboard.c</span><br><span>index c673294..2267ec7 100644</span><br><span>--- a/src/mainboard/sapphire/pureplatinumh61/mainboard.c</span><br><span>+++ b/src/mainboard/sapphire/pureplatinumh61/mainboard.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <device/device.h></span><br><span> #include <drivers/intel/gma/int15.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> static void mainboard_init(struct device *dev)</span><br><span> {</span><br><span>diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c</span><br><span>index 420a956..a20a1f7 100644</span><br><span>--- a/src/mainboard/sapphire/pureplatinumh61/romstage.c</span><br><span>+++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #include <console/console.h></span><br><span> #include "northbridge/intel/sandybridge/sandybridge.h"</span><br><span> #include "northbridge/intel/sandybridge/raminit_native.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "southbridge/intel/bd82x6x/pch.h"</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span>diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c</span><br><span>index 319d81d..3f55140 100644</span><br><span>--- a/src/northbridge/intel/nehalem/early_init.c</span><br><span>+++ b/src/northbridge/intel/nehalem/early_init.c</span><br><span>@@ -25,7 +25,6 @@</span><br><span> #include <cpu/intel/speedstep.h></span><br><span> #include <cpu/intel/turbo.h></span><br><span> #include <arch/cpu.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #include "nehalem.h"</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h</span><br><span>index 33df32f..7a460fc 100644</span><br><span>--- a/src/northbridge/intel/nehalem/nehalem.h</span><br><span>+++ b/src/northbridge/intel/nehalem/nehalem.h</span><br><span>@@ -169,7 +169,6 @@</span><br><span> </span><br><span> #define QUICKPATH_BUS 0xff</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/ibexpeak/pch.h></span><br><span> </span><br><span> /* Everything below this line is ignored in the DSDT */</span><br><span>diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c</span><br><span>index 6a27b57..bd2042e 100644</span><br><span>--- a/src/northbridge/intel/nehalem/raminit.c</span><br><span>+++ b/src/northbridge/intel/nehalem/raminit.c</span><br><span>@@ -56,7 +56,6 @@</span><br><span> </span><br><span> #include "nehalem.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "southbridge/intel/ibexpeak/me.h"</span><br><span> </span><br><span> #if REAL</span><br><span>diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c</span><br><span>index 612e25b..2f1b790 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/early_init.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/early_init.c</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #include <cbmem.h></span><br><span> #include <pc80/mc146818rtc.h></span><br><span> #include <romstage_handoff.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "sandybridge.h"</span><br><span> </span><br><span> static void sandybridge_setup_bars(void)</span><br><span>diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>index e81d3bf..5772962 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>+++ b/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>@@ -59,7 +59,6 @@</span><br><span> #define IOMMU_BASE2 0xfed91000ULL</span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> /* Everything below this line is ignored in the DSDT */</span><br><span> #ifndef __ACPI__</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c</span><br><span>index 0cbf3c6..d5721e6 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/azalia.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/azalia.c</span><br><span>@@ -23,7 +23,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include <delay.h></span><br><span> #include <device/azalia_device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span> #define HDA_ICII_REG 0x68</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c</span><br><span>index b3a1911..8541903 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/bootblock.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/bootblock.c</span><br><span>@@ -15,7 +15,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <cpu/x86/tsc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "southbridge/intel/common/rcba.h"</span><br><span> #include "pch.h"</span><br><span> </span><br><span> static void store_initial_timestamp(void)</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c</span><br><span>index 427e58c..4015495 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_pch.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_pch.c</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #include <device/pci_def.h></span><br><span> #include <delay.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> /* For DMI bar. */</span><br><span> #include "northbridge/intel/sandybridge/sandybridge.h"</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c</span><br><span>index 9ce9dc9..9bd3a26 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_rcba.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_rcba.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include "pch.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "northbridge/intel/sandybridge/sandybridge.h"</span><br><span> </span><br><span> void</span><br><span>@@ -60,9 +59,9 @@</span><br><span> DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);</span><br><span> </span><br><span> /* Enable IOAPIC (generic) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA16(EOIC) = 0x0100;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(OIC) = 0x0100;</span><br><span> /* PCH BWG says to read back the IOAPIC enable register */</span><br><span style="color: hsl(0, 100%, 40%);">- (void) RCBA16(EOIC);</span><br><span style="color: hsl(120, 100%, 40%);">+ (void) RCBA16(OIC);</span><br><span> }</span><br><span> </span><br><span> void</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c</span><br><span>index a9ecd82..1400837 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_spi.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_spi.c</span><br><span>@@ -19,7 +19,6 @@</span><br><span> #include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span> #define SPI_DELAY 10 /* 10us */</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c</span><br><span>index 37df501..a5c63b6 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_thermal.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_thermal.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include "pch.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "cpu/intel/model_206ax/model_206ax.h"</span><br><span> #include <cpu/x86/msr.h></span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c</span><br><span>index 9724f08..06010d7 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/finalize.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/finalize.c</span><br><span>@@ -18,7 +18,7 @@</span><br><span> #include <device/pci_ops.h></span><br><span> #include <console/post_codes.h></span><br><span> #include <cpu/x86/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "pch.h"</span><br><span> #include <spi-generic.h></span><br><span> #include "chip.h"</span><br><span> #include "pch.h"</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>index 109c06e..611b08f 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>@@ -33,7 +33,6 @@</span><br><span> #include <cbmem.h></span><br><span> #include <string.h></span><br><span> #include <cpu/x86/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> #include "nvs.h"</span><br><span> #include <southbridge/intel/common/pciehp.h></span><br><span>diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c</span><br><span>index a5c5e52..70ba301 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/me.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/me.c</span><br><span>@@ -39,7 +39,6 @@</span><br><span> # include <device/pci.h></span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "me.h"</span><br><span> #include "pch.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c</span><br><span>index 0334af3..9011787 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/me_8.x.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/me_8.x.c</span><br><span>@@ -39,7 +39,6 @@</span><br><span> # include <device/pci.h></span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "me.h"</span><br><span> #include "pch.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c</span><br><span>index 73c84bb..0b0fc35 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.c</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> #include <string.h></span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>index d7656b3..3975d0c 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>@@ -45,6 +45,12 @@</span><br><span> #define DEFAULT_GPIOBASE 0x0480</span><br><span> #define DEFAULT_PMBASE 0x0500</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X)</span><br><span> #define CROS_GPIO_DEVICE_NAME "CougarPoint"</span><br><span> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)</span><br><span>@@ -264,6 +270,73 @@</span><br><span> /* Root Complex Register Block */</span><br><span> #define RCBA 0xf0</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA_AND_OR(bits, x, and, or) \</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCH 0x0000 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCAP1 0x0004 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCAP2 0x0008 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PVC 0x000c /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PVS 0x000e /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define V0CAP 0x0010 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define V0CTL 0x0014 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define V0STS 0x001a /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define V1CAP 0x001c /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define V1CTL 0x0020 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define V1STS 0x0026 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCTCL 0x0100 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ESD 0x0104 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ULD 0x0110 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ULBA 0x0118 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP1D 0x0120 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP1BA 0x0128 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP2D 0x0130 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP2BA 0x0138 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP3D 0x0140 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP3BA 0x0148 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP4D 0x0150 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP4BA 0x0158 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDD 0x0160 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDBA 0x0168 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP5D 0x0170 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP5BA 0x0178 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP6D 0x0180 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP6BA 0x0188 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPC 0x0400 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN 0x0404 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Root Port configuratinon space hide */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get the function number assigned to a Root Port */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set the function number for a Root Port */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+/* Root Port function number mask */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_FNMASK(port) (7 << ((port) * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRSR 0x1e00 /* 8bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRCR 0x1e10 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TWDR 0x1e18 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOTR0 0x1e80 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOTR1 0x1e88 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOTR2 0x1e90 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOTR3 0x1e98 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCTL 0x3000 /* 8bit */</span><br><span> </span><br><span> #define NOINT 0</span><br><span> #define INTA 1</span><br><span>@@ -293,9 +366,85 @@</span><br><span> #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))</span><br><span> #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP 0x3100 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_TTIP 24 /* Thermal Throttle Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_SIP2 20 /* SATA Pin 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_SMIP 12 /* SMBUS Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_SIP 8 /* SATA Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D30IP 0x3104 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D30IP_PIP 0 /* PCI Bridge Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D29IP 0x3108 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D29IP_E1P 0 /* EHCI #1 Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP 0x310c /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P8IP 28 /* PCI Express Port 8 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P7IP 24 /* PCI Express Port 7 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P6IP 20 /* PCI Express Port 6 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P5IP 16 /* PCI Express Port 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P4IP 12 /* PCI Express Port 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P3IP 8 /* PCI Express Port 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P2IP 4 /* PCI Express Port 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P1IP 0 /* PCI Express Port 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D27IP 0x3110 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D27IP_ZIP 0 /* HD Audio Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D26IP 0x3114 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D26IP_E2P 0 /* EHCI #2 Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D25IP 0x3118 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D25IP_LIP 0 /* GbE LAN Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP 0x3124 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP_KTIP 12 /* KT Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP_IDERIP 8 /* IDE-R Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP_MEI2IP 4 /* MEI #2 Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP_MEI1IP 0 /* MEI #1 Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D20IP 0x3128 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D20IP_XHCIIP 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IR 0x3140 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D30IR 0x3142 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D29IR 0x3144 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IR 0x3146 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D27IR 0x3148 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D26IR 0x314c /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D25IR 0x3150 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IR 0x315c /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D20IR 0x3160 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define OIC 0x31fe /* 16bit */</span><br><span> #define SOFT_RESET_CTRL 0x38f4</span><br><span> #define SOFT_RESET_DATA 0x38f8</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define DIR_ROUTE(x,a,b,c,d) \</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((b) << DIR_IBR) | ((a) << DIR_IAR))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RC 0x3400 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define HPTC 0x3404 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCS 0x3410 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define BUC 0x3414 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_GBE (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD 0x3418 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPBDF 0x3424 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD2 0x3428 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG 0x341c /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Function Disable 1 RCBA 0x3418 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_P2P (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_SATA1 (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_SMBUS (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_HD_AUDIO (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_EHCI2 (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_LPC (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_EHCI1 (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_PCIE(x) (1 << (16 + x))</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_THERMAL (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_SATA2 (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_XHCI (1 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Function Disable 2 RCBA 0x3428 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_KT (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_IDER (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_MEI2 (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_MEI1 (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_ENABLE_DBDF (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* USB Port Disable Override */</span><br><span> #define USBPDO 0x359c /* 32bit */</span><br><span> /* USB Overcurrent MAP Register */</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c</span><br><span>index 458729d..5605841 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pcie.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pcie.c</span><br><span>@@ -21,7 +21,6 @@</span><br><span> #include <device/pci_ids.h></span><br><span> #include <southbridge/intel/common/pciehp.h></span><br><span> #include <assert.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span> static void pch_pcie_pm_early(struct device *dev)</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c</span><br><span>index e2ff851e..0329795 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/smihandler.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/smihandler.c</span><br><span>@@ -23,7 +23,6 @@</span><br><span> #include <elog.h></span><br><span> #include <halt.h></span><br><span> #include <pc80/mc146818rtc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span> #include "nvs.h"</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c</span><br><span>index 7362dbd..996c89c 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/usb_ehci.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c</span><br><span>@@ -18,7 +18,6 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> #include <device/pci_ehci.h></span><br><span> #include <arch/io.h></span><br><span>diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h</span><br><span>deleted file mode 100644</span><br><span>index ad8285a..0000000</span><br><span>--- a/src/southbridge/intel/common/rcba.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,220 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H</span><br><span style="color: hsl(0, 100%, 40%);">-#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * The DnnIR registers use common RCBA offsets across these chipsets:</span><br><span style="color: hsl(0, 100%, 40%);">- * bd82x6x, i82801, i89xx, ibexpeak, lynxpoint</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * However not all registers are in use on all of these.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x)))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA_AND_OR(bits, x, and, or) \</span><br><span style="color: hsl(0, 100%, 40%);">- (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCH 0x0000 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCAP1 0x0004 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCAP2 0x0008 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PVC 0x000c /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PVS 0x000e /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define V0CAP 0x0010 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define V0CTL 0x0014 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define V0STS 0x001a /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define V1CAP 0x001c /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define V1CTL 0x0020 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define V1STS 0x0026 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCTCL 0x0100 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define ESD 0x0104 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define ULD 0x0110 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define ULBA 0x0118 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP1D 0x0120 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP1BA 0x0128 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP2D 0x0130 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP2BA 0x0138 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP3D 0x0140 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP3BA 0x0148 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP4D 0x0150 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP4BA 0x0158 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDD 0x0160 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDBA 0x0168 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP5D 0x0170 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP5BA 0x0178 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP6D 0x0180 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP6BA 0x0188 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RPC 0x0400 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RPFN 0x0404 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Root Port configuratinon space hide */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))</span><br><span style="color: hsl(0, 100%, 40%);">-/* Get the function number assigned to a Root Port */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RPFN_FNGET(reg, port) (((reg) >> ((port) * 4)) & 7)</span><br><span style="color: hsl(0, 100%, 40%);">-/* Set the function number for a Root Port */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RPFN_FNSET(port, func) (((func) & 7) << ((port) * 4))</span><br><span style="color: hsl(0, 100%, 40%);">-/* Root Port function number mask */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RPFN_FNMASK(port) (7 << ((port) * 4))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRSR 0x1e00 /* 8bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRCR 0x1e10 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define TWDR 0x1e18 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define IOTR0 0x1e80 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IOTR1 0x1e88 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IOTR2 0x1e90 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IOTR3 0x1e98 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCTL 0x3000 /* 8bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31IP 0x3100 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31IP_TTIP 24 /* Thermal Throttle Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31IP_SIP2 20 /* SATA Pin 2 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31IP_SMIP 12 /* SMBUS Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31IP_SIP 8 /* SATA Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D30IP 0x3104 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D30IP_PIP 0 /* PCI Bridge Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D29IP 0x3108 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D29IP_E1P 0 /* EHCI #1 Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP 0x310c /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P8IP 28 /* PCI Express Port 8 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P7IP 24 /* PCI Express Port 7 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P6IP 20 /* PCI Express Port 6 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P5IP 16 /* PCI Express Port 5 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P4IP 12 /* PCI Express Port 4 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P3IP 8 /* PCI Express Port 3 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P2IP 4 /* PCI Express Port 2 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P1IP 0 /* PCI Express Port 1 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D27IP 0x3110 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D27IP_ZIP 0 /* HD Audio Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D26IP 0x3114 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D26IP_E2P 0 /* EHCI #2 Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D25IP 0x3118 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D25IP_LIP 0 /* GbE LAN Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D22IP 0x3124 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D22IP_KTIP 12 /* KT Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D22IP_IDERIP 8 /* IDE-R Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D22IP_MEI2IP 4 /* MEI #2 Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D22IP_MEI1IP 0 /* MEI #1 Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D20IP 0x3128 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D20IP_XHCIIP 0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31IR 0x3140 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D30IR 0x3142 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D29IR 0x3144 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IR 0x3146 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D27IR 0x3148 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D26IR 0x314c /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D25IR 0x3150 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D23IR 0x3158 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D22IR 0x315c /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D21IR 0x3164 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D20IR 0x3160 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D19IR 0x3168 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define EOIC 0x31fe /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define OIC 0x31ff /* 8bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define DIR_ROUTE(x, a, b, c, d) \</span><br><span style="color: hsl(0, 100%, 40%);">- (RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \</span><br><span style="color: hsl(0, 100%, 40%);">- ((b) << DIR_IBR) | ((a) << DIR_IAR)))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RC 0x3400 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define HPTC 0x3404 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GCS 0x3410 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define BUC 0x3414 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_GBE (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD 0x3418 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPBDF 0x3424 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD2 0x3428 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG 0x341c /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Function Disable 1 RCBA 0x3418 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_P2P (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_SATA1 (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_SMBUS (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_HD_AUDIO (1 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_EHCI2 (1 << 13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_LPC (1 << 14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_EHCI1 (1 << 15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_PCIE(x) (1 << (16 + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_THERMAL (1 << 24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_SATA2 (1 << 25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_XHCI (1 << 27)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Function Disable 2 RCBA 0x3428 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_KT (1 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_IDER (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_MEI2 (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_MEI1 (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_ENABLE_DBDF (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Function Disable (FD) register values.</span><br><span style="color: hsl(0, 100%, 40%);">- * Setting a bit disables the corresponding</span><br><span style="color: hsl(0, 100%, 40%);">- * feature.</span><br><span style="color: hsl(0, 100%, 40%);">- * Not all features might be disabled on</span><br><span style="color: hsl(0, 100%, 40%);">- * all chipsets. Esp. ICH-7U is picky.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_PCIE6 (1 << 21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_PCIE5 (1 << 20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_PCIE4 (1 << 19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_PCIE3 (1 << 18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_PCIE2 (1 << 17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_PCIE1 (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_EHCI (1 << 15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_LPCB (1 << 14)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* UHCI must be disabled from 4 downwards.</span><br><span style="color: hsl(0, 100%, 40%);">- * If UHCI controllers get disabled, EHCI</span><br><span style="color: hsl(0, 100%, 40%);">- * must know about it, too! */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_UHCI4 (1 << 11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_UHCI34 ((1 << 10) | FD_UHCI4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_UHCI234 ((1 << 9) | FD_UHCI3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_UHCI1234 ((1 << 8) | FD_UHCI2)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_INTLAN (1 << 7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_ACMOD (1 << 6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_ACAUD (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_HDAUD (1 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_SMBUS (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_SATA (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_PATA (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* __ACPI__ */</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */</span><br><span>diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c</span><br><span>index d27c451..7f97971 100644</span><br><span>--- a/src/southbridge/intel/common/rcba_pirq.c</span><br><span>+++ b/src/southbridge/intel/common/rcba_pirq.c</span><br><span>@@ -17,7 +17,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <southbridge/intel/common/acpi_pirq_gen.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba_pirq.h></span><br><span> </span><br><span> #define MAX_SLOT 31</span><br><span> #define MIN_SLOT 19</span><br><span>diff --git a/src/southbridge/intel/common/rcba_pirq.h b/src/southbridge/intel/common/rcba_pirq.h</span><br><span>new file mode 100644</span><br><span>index 0000000..cf76fb3</span><br><span>--- /dev/null</span><br><span>+++ b/src/southbridge/intel/common/rcba_pirq.h</span><br><span>@@ -0,0 +1,44 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The DnnIR registers use common RCBA offsets across these chipsets:</span><br><span style="color: hsl(120, 100%, 40%);">+ * bd82x6x, i82801, i89xx, ibexpeak, lynxpoint</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * However not all registers are in use on all of these.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IR 0x3140 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D30IR 0x3142 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D29IR 0x3144 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IR 0x3146 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D27IR 0x3148 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D26IR 0x314c /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D25IR 0x3150 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D23IR 0x3158 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IR 0x315c /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D21IR 0x3164 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D20IR 0x3160 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D19IR 0x3168 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x))))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c</span><br><span>index 61cd835..9e3ed43 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/azalia.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/azalia.c</span><br><span>@@ -23,7 +23,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include <delay.h></span><br><span> #include <device/azalia_device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span> #define HDA_ICII_REG 0x68</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c</span><br><span>index 7d025cc..b09951f 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/lpc.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/lpc.c</span><br><span>@@ -36,7 +36,6 @@</span><br><span> #include "nvs.h"</span><br><span> #include <southbridge/intel/common/pciehp.h></span><br><span> #include <southbridge/intel/common/acpi_pirq_gen.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #define NMI_OFF 0</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c</span><br><span>index 92cba81..0d75350 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/me.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/me.c</span><br><span>@@ -30,7 +30,6 @@</span><br><span> #include <string.h></span><br><span> #include <delay.h></span><br><span> #include <elog.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #ifdef __SMM__</span><br><span> #include <arch/io.h></span><br><span>diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>index 4e86c82..8012a75 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/pch.h</span><br><span>+++ b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>@@ -47,6 +47,12 @@</span><br><span> #define DEFAULT_PMBASE 0x0500</span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span> </span><br><span> #if defined(__SMM__) && !defined(__ASSEMBLER__)</span><br><span>@@ -235,6 +241,75 @@</span><br><span> </span><br><span> /* Root Complex Register Block */</span><br><span> #define RCBA 0xf0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA_AND_OR(bits, x, and, or) \</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCH 0x0000 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCAP1 0x0004 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCAP2 0x0008 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PVC 0x000c /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PVS 0x000e /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define V0CAP 0x0010 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define V0CTL 0x0014 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define V0STS 0x001a /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define V1CAP 0x001c /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define V1CTL 0x0020 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define V1STS 0x0026 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCTCL 0x0100 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ESD 0x0104 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ULD 0x0110 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ULBA 0x0118 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP1D 0x0120 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP1BA 0x0128 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP2D 0x0130 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP2BA 0x0138 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP3D 0x0140 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP3BA 0x0148 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP4D 0x0150 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP4BA 0x0158 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDD 0x0160 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDBA 0x0168 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP5D 0x0170 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP5BA 0x0178 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP6D 0x0180 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP6BA 0x0188 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPC 0x0400 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN 0x0404 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Root Port configuratinon space hide */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get the function number assigned to a Root Port */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set the function number for a Root Port */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+/* Root Port function number mask */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_FNMASK(port) (7 << ((port) * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRSR 0x1e00 /* 8bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRCR 0x1e10 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TWDR 0x1e18 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOTR0 0x1e80 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOTR1 0x1e88 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOTR2 0x1e90 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOTR3 0x1e98 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCTL 0x3000 /* 8bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define NOINT 0</span><br><span> #define INTA 1</span><br><span> #define INTB 2</span><br><span>@@ -263,9 +338,86 @@</span><br><span> #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))</span><br><span> #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP 0x3100 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_TTIP 24 /* Thermal Throttle Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_SIP2 20 /* SATA Pin 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_UNKIP 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_SMIP 12 /* SMBUS Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_SIP 8 /* SATA Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D30IP 0x3104 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D30IP_PIP 0 /* PCI Bridge Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D29IP 0x3108 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D29IP_E1P 0 /* EHCI #1 Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP 0x310c /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P8IP 28 /* PCI Express Port 8 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P7IP 24 /* PCI Express Port 7 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P6IP 20 /* PCI Express Port 6 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P5IP 16 /* PCI Express Port 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P4IP 12 /* PCI Express Port 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P3IP 8 /* PCI Express Port 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P2IP 4 /* PCI Express Port 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P1IP 0 /* PCI Express Port 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D27IP 0x3110 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D27IP_ZIP 0 /* HD Audio Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D26IP 0x3114 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D26IP_E2P 0 /* EHCI #2 Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D25IP 0x3118 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D25IP_LIP 0 /* GbE LAN Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP 0x3124 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP_KTIP 12 /* KT Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP_IDERIP 8 /* IDE-R Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP_MEI2IP 4 /* MEI #2 Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP_MEI1IP 0 /* MEI #1 Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D20IP 0x3128 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D20IP_XHCIIP 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IR 0x3140 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D30IR 0x3142 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D29IR 0x3144 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IR 0x3146 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D27IR 0x3148 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D26IR 0x314c /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D25IR 0x3150 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IR 0x315c /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D20IR 0x3160 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define OIC 0x31fe /* 16bit */</span><br><span> #define SOFT_RESET_CTRL 0x38f4</span><br><span> #define SOFT_RESET_DATA 0x38f8</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define DIR_ROUTE(x,a,b,c,d) \</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((b) << DIR_IBR) | ((a) << DIR_IAR))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RC 0x3400 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define HPTC 0x3404 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCS 0x3410 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define BUC 0x3414 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_GBE (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD 0x3418 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPBDF 0x3424 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD2 0x3428 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG 0x341c /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Function Disable 1 RCBA 0x3418 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_P2P (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_SATA1 (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_SMBUS (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_HD_AUDIO (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_EHCI2 (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_LPC (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_EHCI1 (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_PCIE(x) (1 << (16 + x))</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_THERMAL (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_SATA2 (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_XHCI (1 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Function Disable 2 RCBA 0x3428 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_KT (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_IDER (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_MEI2 (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_MEI1 (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_ENABLE_DBDF (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* ICH7 PMBASE */</span><br><span> #define PM1_STS 0x00</span><br><span> #define WAK_STS (1 << 15)</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c</span><br><span>index 12a7ac0..380c241 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/smihandler.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/smihandler.c</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #include <halt.h></span><br><span> #include <pc80/mc146818rtc.h></span><br><span> #include "pch.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #include "nvs.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c</span><br><span>index 51a6203..13670b8 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/usb_ehci.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c</span><br><span>@@ -22,7 +22,6 @@</span><br><span> #include "pch.h"</span><br><span> #include <device/pci_ehci.h></span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> static void usb_ehci_init(struct device *dev)</span><br><span> {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27038">change 27038</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 </div>
<div style="display:none"> Gerrit-Change-Number: 27038 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>