<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27028">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek: Refactor to sharing mtcmos code among similar SOCs<br><br>This patch refactor mtcmos code which will be reused among similar SOCs.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=the refactored code works fine on the new platform (with the rest<br> of the patches applied) and Elm platform<br><br>Change-Id: Ibfd0a90f6eba3ed2e74a3fd54279c7645aa41774<br>Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com><br>---<br>M src/soc/mediatek/mt8173/dramc_pi_basic_api.c<br>M src/soc/mediatek/mt8173/include/soc/mtcmos.h<br>M src/soc/mediatek/mt8173/include/soc/spm.h<br>M src/soc/mediatek/mt8173/mtcmos.c<br>4 files changed, 58 insertions(+), 35 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/27028/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c</span><br><span>index e471b4f..cb6cc2c 100644</span><br><span>--- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c</span><br><span>+++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c</span><br><span>@@ -381,15 +381,15 @@</span><br><span> }</span><br><span> </span><br><span> /* mempll new power-on */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_spm->poweron_config_set, 0x1 << 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_spm->poweron_config_set, 0x1 << 0 |</span><br><span> SPM_PROJECT_CODE << 16);</span><br><span> /* request mempll reset/pdn mode */</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&mt8173_spm->power_on_val0, 0x1 << 27);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_spm->power_on_val0, 0x1 << 27);</span><br><span> </span><br><span> udelay(2);</span><br><span> </span><br><span> /* unrequest mempll reset/pdn mode and wait settle */</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&mt8173_spm->power_on_val0, 0x1 << 27);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&mtk_spm->power_on_val0, 0x1 << 27);</span><br><span> </span><br><span> udelay(31); /* PLL ready */</span><br><span> </span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/mtcmos.h b/src/soc/mediatek/mt8173/include/soc/mtcmos.h</span><br><span>index a2b4f65..1b2c489 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/mtcmos.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/mtcmos.h</span><br><span>@@ -13,9 +13,9 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __SOC_MEDIATEK_MT8173_MTCMOS_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __SOC_MEDIATEK_MT8173_MTCMOS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __SOC_MEDIATEK_COMMON_MTCMOS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __SOC_MEDIATEK_COMMON_MTCMOS_H__</span><br><span> </span><br><span> void mtcmos_audio_power_on(void);</span><br><span> void mtcmos_display_power_on(void);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* __SOC_MEDIATEK_MT8173_MTCMOS_H__ */</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __SOC_MEDIATEK_COMMON_MTCMOS_H__ */</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h</span><br><span>index 77516fc..698e6b8 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/spm.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/spm.h</span><br><span>@@ -23,7 +23,14 @@</span><br><span> SPM_PROJECT_CODE = 0xb16</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-struct mt8173_spm_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DISP_SRAM_PDN_MASK = 0xf << 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ DISP_SRAM_ACK_MASK = 0x1 << 12,</span><br><span style="color: hsl(120, 100%, 40%);">+ AUD_SRAM_PDN_MASK = 0xf << 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ AUD_SRAM_ACK_MASK = 0xf << 12,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mtk_spm_regs {</span><br><span> u32 poweron_config_set;</span><br><span> u32 reserved1[3];</span><br><span> u32 power_on_val0; /* 0x010 */</span><br><span>@@ -152,8 +159,8 @@</span><br><span> u32 sleep_ca15_wfi_en[4];</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-check_member(mt8173_spm_regs, sleep_ca15_wfi_en[3], 0xf1c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, sleep_ca15_wfi_en[3], 0xf1c);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct mt8173_spm_regs *const mt8173_spm = (void *)SPM_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;</span><br><span> </span><br><span> #endif /* __SOC_MEDIATEK_MT8173_SPM_H__ */</span><br><span>diff --git a/src/soc/mediatek/mt8173/mtcmos.c b/src/soc/mediatek/mt8173/mtcmos.c</span><br><span>index cdd31f4..f5b6e46 100644</span><br><span>--- a/src/soc/mediatek/mt8173/mtcmos.c</span><br><span>+++ b/src/soc/mediatek/mt8173/mtcmos.c</span><br><span>@@ -13,10 +13,19 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stddef.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #include <arch/io.h></span><br><span> #include <soc/mtcmos.h></span><br><span> #include <soc/spm.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+struct power_domain_data {</span><br><span style="color: hsl(120, 100%, 40%);">+ void *pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pwr_sta_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sram_pdn_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sram_ack_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> enum {</span><br><span> SRAM_ISOINT_B = 1U << 6,</span><br><span> SRAM_CKISO = 1U << 5,</span><br><span>@@ -28,44 +37,51 @@</span><br><span> };</span><br><span> </span><br><span> enum {</span><br><span style="color: hsl(0, 100%, 40%);">- SRAM_PDN = 0xf << 8,</span><br><span style="color: hsl(0, 100%, 40%);">- DIS_SRAM_ACK = 0x1 << 12,</span><br><span style="color: hsl(0, 100%, 40%);">- AUD_SRAM_ACK = 0xf << 12,</span><br><span style="color: hsl(120, 100%, 40%);">+ DISP_PWR_STA_MASK = 0x1 << 3,</span><br><span style="color: hsl(120, 100%, 40%);">+ AUD_PWR_STA_MASK = 0x1 << 24,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-enum {</span><br><span style="color: hsl(0, 100%, 40%);">- DIS_PWR_STA_MASK = 0x1 << 3,</span><br><span style="color: hsl(0, 100%, 40%);">- AUD_PWR_STA_MASK = 0x1 << 24,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void mtcmos_power_on(u32 *pwr_con, u32 pwr_sta_mask)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mtcmos_power_on(const struct power_domain_data *pd)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_spm->poweron_config_set,</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_spm->poweron_config_set,</span><br><span> (SPM_PROJECT_CODE << 16) | (1U << 0));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(pwr_con, PWR_ON);</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(pwr_con, PWR_ON_2ND);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(pd->pwr_con, PWR_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(pd->pwr_con, PWR_ON_2ND);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- while (!(read32(&mt8173_spm->pwr_status) & pwr_sta_mask) ||</span><br><span style="color: hsl(0, 100%, 40%);">- !(read32(&mt8173_spm->pwr_status_2nd) & pwr_sta_mask))</span><br><span style="color: hsl(120, 100%, 40%);">+ while (!(read32(&mtk_spm->pwr_status) & pd->pwr_sta_mask) ||</span><br><span style="color: hsl(120, 100%, 40%);">+ !(read32(&mtk_spm->pwr_status_2nd) & pd->pwr_sta_mask))</span><br><span> continue;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(pwr_con, PWR_CLK_DIS);</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(pwr_con, PWR_ISO);</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(pwr_con, PWR_RST_B);</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(pwr_con, SRAM_PDN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(pd->pwr_con, PWR_CLK_DIS);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(pd->pwr_con, PWR_ISO);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(pd->pwr_con, PWR_RST_B);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(pd->pwr_con, pd->sram_pdn_mask);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void mtcmos_audio_power_on(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- mtcmos_power_on(&mt8173_spm->audio_pwr_con, AUD_PWR_STA_MASK);</span><br><span style="color: hsl(0, 100%, 40%);">- while (read32(&mt8173_spm->audio_pwr_con) & AUD_SRAM_ACK)</span><br><span style="color: hsl(120, 100%, 40%);">+ while (read32(pd->pwr_con) & pd->sram_ack_mask)</span><br><span> continue;</span><br><span> }</span><br><span> </span><br><span> void mtcmos_display_power_on(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- mtcmos_power_on(&mt8173_spm->dis_pwr_con, DIS_PWR_STA_MASK);</span><br><span style="color: hsl(0, 100%, 40%);">- while (read32(&mt8173_spm->dis_pwr_con) & DIS_SRAM_ACK)</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(120, 100%, 40%);">+ static const struct power_domain_data disp = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .pwr_con = &mtk_spm->dis_pwr_con,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pwr_sta_mask = DISP_PWR_STA_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ .sram_pdn_mask = DISP_SRAM_PDN_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ .sram_ack_mask = DISP_SRAM_ACK_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mtcmos_power_on(&disp);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mtcmos_audio_power_on(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static const struct power_domain_data audio = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .pwr_con = &mtk_spm->audio_pwr_con,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pwr_sta_mask = AUD_PWR_STA_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ .sram_pdn_mask = AUD_SRAM_PDN_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ .sram_ack_mask = AUD_SRAM_ACK_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mtcmos_power_on(&audio);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27028">change 27028</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27028"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibfd0a90f6eba3ed2e74a3fd54279c7645aa41774 </div>
<div style="display:none"> Gerrit-Change-Number: 27028 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>