<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27056">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">gma registers: Separate 32- and 64-bit GTT access<br><br>With Broadwell the GTT layout changed significantly. Before, we had a<br>2MiB GTT with 32-bit entries. Now, it's a 8MiB GTT with 64-bit entries.<br>We used to abstract over that with configuration constants but that's<br>infeasible if we want to support Haswell and Broadwell with a single<br>binary (boards that support both processors exist).<br><br>Therefore, declare both GTT variants and decide based on the CPU which<br>one to use.<br><br>Change-Id: Ib6f21b71c434a9cbdd5cdfa3697da2b2e86750f4<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M common/hw-gfx-gma-config.ads.template<br>M common/hw-gfx-gma-registers.adb<br>M common/hw-gfx-gma-registers.ads<br>M common/hw-gfx-gma.adb<br>4 files changed, 48 insertions(+), 33 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/56/27056/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template</span><br><span>index d082a1b..9c89ac2 100644</span><br><span>--- a/common/hw-gfx-gma-config.ads.template</span><br><span>+++ b/common/hw-gfx-gma-config.ads.template</span><br><span>@@ -135,7 +135,7 @@</span><br><span> Has_Per_Pipe_SRD : constant Boolean := CPU >= Broadwell;</span><br><span> </span><br><span> ----- GTT: -------------</span><br><span style="color: hsl(0, 100%, 40%);">- Fold_39Bit_GTT_PTE : constant Boolean := CPU <= Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_64bit_GTT : constant Boolean := CPU >= Broadwell;</span><br><span> </span><br><span> ----------------------------------------------------------------------------</span><br><span> </span><br><span>@@ -252,19 +252,7 @@</span><br><span> </span><br><span> ----------------------------------------------------------------------------</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- GTT_Offset : constant := (case CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 .. Haswell => 16#0020_0000#,</span><br><span style="color: hsl(0, 100%, 40%);">- when Broadwell .. Skylake => 16#0080_0000#);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- GTT_Size : constant := (case CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 .. Haswell => 16#0020_0000#,</span><br><span style="color: hsl(0, 100%, 40%);">- -- Limit Broadwell to 4MiB to have a stable</span><br><span style="color: hsl(0, 100%, 40%);">- -- interface (i.e. same number of entries):</span><br><span style="color: hsl(0, 100%, 40%);">- when Broadwell .. Skylake => 16#0040_0000#);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- GTT_PTE_Size : constant := (case CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 .. Haswell => 4,</span><br><span style="color: hsl(0, 100%, 40%);">- when Broadwell .. Skylake => 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_PTE_Size : constant := (if Has_64bit_GTT then 8 else 4);</span><br><span> </span><br><span> Fence_Base : constant := (case CPU is</span><br><span> when G45 .. Ironlake => 16#0000_3000#,</span><br><span>diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb</span><br><span>index fa53ebf..368b259 100644</span><br><span>--- a/common/hw-gfx-gma-registers.adb</span><br><span>+++ b/common/hw-gfx-gma-registers.adb</span><br><span>@@ -26,9 +26,10 @@</span><br><span> package body HW.GFX.GMA.Registers</span><br><span> with</span><br><span> Refined_State =></span><br><span style="color: hsl(0, 100%, 40%);">- (Address_State => (Regs.Base_Address, GTT.Base_Address),</span><br><span style="color: hsl(120, 100%, 40%);">+ (Address_State =></span><br><span style="color: hsl(120, 100%, 40%);">+ (Regs.Base_Address, GTT_32.Base_Address, GTT_64.Base_Address),</span><br><span> Register_State => Regs.State,</span><br><span style="color: hsl(0, 100%, 40%);">- GTT_State => GTT.State)</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_State => (GTT_32.State, GTT_64.State))</span><br><span> is</span><br><span> pragma Disable_Atomic_Synchronization;</span><br><span> </span><br><span>@@ -46,16 +47,27 @@</span><br><span> </span><br><span> ----------------------------------------------------------------------------</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- type GTT_PTE_Type is mod 2 ** (Config.GTT_PTE_Size * 8);</span><br><span style="color: hsl(0, 100%, 40%);">- type GTT_Registers_Type is array (GTT_Range) of GTT_PTE_Type</span><br><span style="color: hsl(120, 100%, 40%);">+ type GTT_PTE_32 is mod 2 ** 32;</span><br><span style="color: hsl(120, 100%, 40%);">+ type GTT_Registers_32 is array (GTT_Range) of GTT_PTE_32</span><br><span> with</span><br><span> Volatile_Components,</span><br><span style="color: hsl(0, 100%, 40%);">- Size => Config.GTT_Size * 8;</span><br><span style="color: hsl(0, 100%, 40%);">- package GTT is new MMIO_Range</span><br><span style="color: hsl(0, 100%, 40%);">- (Base_Addr => Config.Default_MMIO_Base + Config.GTT_Offset,</span><br><span style="color: hsl(0, 100%, 40%);">- Element_T => GTT_PTE_Type,</span><br><span style="color: hsl(120, 100%, 40%);">+ Size => MMIO_GTT_32_Size * 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ package GTT_32 is new MMIO_Range</span><br><span style="color: hsl(120, 100%, 40%);">+ (Base_Addr => Config.Default_MMIO_Base + MMIO_GTT_32_Offset,</span><br><span style="color: hsl(120, 100%, 40%);">+ Element_T => GTT_PTE_32,</span><br><span> Index_T => GTT_Range,</span><br><span style="color: hsl(0, 100%, 40%);">- Array_T => GTT_Registers_Type);</span><br><span style="color: hsl(120, 100%, 40%);">+ Array_T => GTT_Registers_32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ type GTT_PTE_64 is mod 2 ** 64;</span><br><span style="color: hsl(120, 100%, 40%);">+ type GTT_Registers_64 is array (GTT_Range) of GTT_PTE_64</span><br><span style="color: hsl(120, 100%, 40%);">+ with</span><br><span style="color: hsl(120, 100%, 40%);">+ Volatile_Components,</span><br><span style="color: hsl(120, 100%, 40%);">+ Size => MMIO_GTT_64_Size * 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ package GTT_64 is new MMIO_Range</span><br><span style="color: hsl(120, 100%, 40%);">+ (Base_Addr => Config.Default_MMIO_Base + MMIO_GTT_64_Offset,</span><br><span style="color: hsl(120, 100%, 40%);">+ Element_T => GTT_PTE_64,</span><br><span style="color: hsl(120, 100%, 40%);">+ Index_T => GTT_Range,</span><br><span style="color: hsl(120, 100%, 40%);">+ Array_T => GTT_Registers_64);</span><br><span> </span><br><span> GTT_PTE_Valid : constant Word32 := 1;</span><br><span> </span><br><span>@@ -150,17 +162,17 @@</span><br><span> Valid : Boolean)</span><br><span> is</span><br><span> begin</span><br><span style="color: hsl(0, 100%, 40%);">- if Config.Fold_39Bit_GTT_PTE then</span><br><span style="color: hsl(0, 100%, 40%);">- GTT.Write</span><br><span style="color: hsl(120, 100%, 40%);">+ if Config.Has_64bit_GTT then</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_32.Write</span><br><span> (Index => GTT_Page,</span><br><span style="color: hsl(0, 100%, 40%);">- Value => GTT_PTE_Type (Device_Address and 16#ffff_f000#) or</span><br><span style="color: hsl(0, 100%, 40%);">- GTT_PTE_Type (Shift_Right (Word64 (Device_Address), 32 - 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Value => GTT_PTE_32 (Device_Address and 16#ffff_f000#) or</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_PTE_32 (Shift_Right (Word64 (Device_Address), 32 - 4)</span><br><span> and 16#0000_07f0#) or</span><br><span> Boolean'Pos (Valid));</span><br><span> else</span><br><span style="color: hsl(0, 100%, 40%);">- GTT.Write</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_64.Write</span><br><span> (Index => GTT_Page,</span><br><span style="color: hsl(0, 100%, 40%);">- Value => GTT_PTE_Type (Device_Address and 16#7f_ffff_f000#) or</span><br><span style="color: hsl(120, 100%, 40%);">+ Value => GTT_PTE_64 (Device_Address and 16#7f_ffff_f000#) or</span><br><span> Boolean'Pos (Valid));</span><br><span> end if;</span><br><span> end Write_GTT;</span><br><span>@@ -378,9 +390,11 @@</span><br><span> begin</span><br><span> Regs.Set_Base_Address (Base);</span><br><span> if GTT_Base = 0 then</span><br><span style="color: hsl(0, 100%, 40%);">- GTT.Set_Base_Address (Base + Config.GTT_Offset);</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_32.Set_Base_Address (Base + MMIO_GTT_32_Offset);</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_64.Set_Base_Address (Base + MMIO_GTT_64_Offset);</span><br><span> else</span><br><span style="color: hsl(0, 100%, 40%);">- GTT.Set_Base_Address (GTT_Base);</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_32.Set_Base_Address (GTT_Base);</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_64.Set_Base_Address (GTT_Base);</span><br><span> end if;</span><br><span> end Set_Register_Base;</span><br><span> </span><br><span>diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads</span><br><span>index 1220d1a..99efba9 100644</span><br><span>--- a/common/hw-gfx-gma-registers.ads</span><br><span>+++ b/common/hw-gfx-gma-registers.ads</span><br><span>@@ -23,6 +23,15 @@</span><br><span> (GTT_State with External, Part_Of => GMA.Device_State)),</span><br><span> Initializes => Address_State</span><br><span> is</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ MMIO_GTT_32_Size : constant := 16#20_0000#;</span><br><span style="color: hsl(120, 100%, 40%);">+ MMIO_GTT_32_Offset : constant := 16#20_0000#;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ -- Limit Broadwell+ to 4MiB to have a stable</span><br><span style="color: hsl(120, 100%, 40%);">+ -- interface (i.e. same number of entries):</span><br><span style="color: hsl(120, 100%, 40%);">+ MMIO_GTT_64_Size : constant := 16#40_0000#;</span><br><span style="color: hsl(120, 100%, 40%);">+ MMIO_GTT_64_Offset : constant := 16#80_0000#;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> type Registers_Invalid_Index is</span><br><span> (Invalid_Register, -- Allow a placeholder when access is not acceptable</span><br><span> </span><br><span>diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb</span><br><span>index f9ca13f..ad686c3 100644</span><br><span>--- a/common/hw-gfx-gma.adb</span><br><span>+++ b/common/hw-gfx-gma.adb</span><br><span>@@ -386,6 +386,10 @@</span><br><span> is</span><br><span> use type HW.Word64;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ function MMIO_GTT_Offset return Natural is</span><br><span style="color: hsl(120, 100%, 40%);">+ (if Config.Has_64bit_GTT</span><br><span style="color: hsl(120, 100%, 40%);">+ then Registers.MMIO_GTT_64_Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ else Registers.MMIO_GTT_32_Offset);</span><br><span> PCI_MMIO_Base, PCI_GTT_Base : Word64;</span><br><span> </span><br><span> Now : constant Time.T := Time.Now;</span><br><span>@@ -447,8 +451,8 @@</span><br><span> Dev.Initialize (Success);</span><br><span> </span><br><span> if Success then</span><br><span style="color: hsl(0, 100%, 40%);">- Dev.Map (PCI_MMIO_Base, PCI.Res0, Length => Config.GTT_Offset);</span><br><span style="color: hsl(0, 100%, 40%);">- Dev.Map (PCI_GTT_Base, PCI.Res0, Offset => Config.GTT_Offset);</span><br><span style="color: hsl(120, 100%, 40%);">+ Dev.Map (PCI_MMIO_Base, PCI.Res0, Length => MMIO_GTT_Offset);</span><br><span style="color: hsl(120, 100%, 40%);">+ Dev.Map (PCI_GTT_Base, PCI.Res0, Offset => MMIO_GTT_Offset);</span><br><span> if PCI_MMIO_Base /= 0 and PCI_GTT_Base /= 0 then</span><br><span> Registers.Set_Register_Base (PCI_MMIO_Base, PCI_GTT_Base);</span><br><span> else</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27056">change 27056</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27056"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: libgfxinit </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib6f21b71c434a9cbdd5cdfa3697da2b2e86750f4 </div>
<div style="display:none"> Gerrit-Change-Number: 27056 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>