<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27060">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">gma config: Introduce per generation/CPU booleans<br><br>The per CPU booleans are additionally guarded by the respective<br>generation so that the compiler may decide purely on the generation.<br>Also use the new booleans to get rid of all direct references to<br>`Config.CPU` and `Config.CPU_Var`.<br><br>Change-Id: I307d1dd56f480fdb4fbc6e2e25fc5f413c4158f8<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M common/hw-gfx-gma-config.ads.template<br>M common/hw-gfx-gma.adb<br>2 files changed, 119 insertions(+), 112 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/60/27060/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template</span><br><span>index 1a0beac..659832f 100644</span><br><span>--- a/common/hw-gfx-gma-config.ads.template</span><br><span>+++ b/common/hw-gfx-gma-config.ads.template</span><br><span>@@ -37,6 +37,30 @@</span><br><span> </span><br><span> ----------------------------------------------------------------------------</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ Gen_G45 : constant Boolean := Gen = G45;</span><br><span style="color: hsl(120, 100%, 40%);">+ Gen_Ironlake : constant Boolean := Gen = Ironlake;</span><br><span style="color: hsl(120, 100%, 40%);">+ Gen_Haswell : constant Boolean := Gen = Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Gen_Broxton : constant Boolean := Gen = Broxton;</span><br><span style="color: hsl(120, 100%, 40%);">+ Gen_Skylake : constant Boolean := Gen = Skylake;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Haswell_Plus : constant Boolean := Gen >= Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Broxton_Plus : constant Boolean := Gen >= Broxton;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU_Ironlake : constant Boolean := Gen_Ironlake and then CPU = Ironlake;</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU_Sandybridge : constant Boolean := Gen_Ironlake and then CPU = Sandybridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU_Ivybridge : constant Boolean := Gen_Ironlake and then CPU = Ivybridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU_Haswell : constant Boolean := Gen_Haswell and then CPU = Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU_Broadwell : constant Boolean := Gen_Haswell and then CPU = Broadwell;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Sandybridge_Plus : constant Boolean :=</span><br><span style="color: hsl(120, 100%, 40%);">+ ((Gen_Ironlake and then CPU >= Sandybridge) or Haswell_Plus);</span><br><span style="color: hsl(120, 100%, 40%);">+ Ivybridge_Plus : constant Boolean :=</span><br><span style="color: hsl(120, 100%, 40%);">+ ((Gen_Ironlake and then CPU >= Ivybridge) or Haswell_Plus);</span><br><span style="color: hsl(120, 100%, 40%);">+ Broadwell_Plus : constant Boolean :=</span><br><span style="color: hsl(120, 100%, 40%);">+ ((Gen_Haswell and then CPU >= Broadwell) or Broxton_Plus);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ----------------------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> Have_HDMI_Buf_Override : constant Boolean :=</span><br><span> DDI_HDMI_Buffer_Translation /= -1;</span><br><span> Default_MMIO_Base_Set : constant Boolean := Default_MMIO_Base /= 0;</span><br><span>@@ -45,25 +69,26 @@</span><br><span> Internal_Is_LVDS : constant Boolean := Internal_Display = LVDS;</span><br><span> Internal_Is_EDP : constant Boolean := Internal_Display = DP;</span><br><span> Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Presence_Straps : constant Boolean := Gen /= Broxton;</span><br><span style="color: hsl(0, 100%, 40%);">- Is_ULT : constant Boolean := CPU_Var = ULT;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Presence_Straps : constant Boolean := not Gen_Broxton;</span><br><span style="color: hsl(120, 100%, 40%);">+ Is_ULT : constant Boolean :=</span><br><span style="color: hsl(120, 100%, 40%);">+ ((Gen_Haswell or Gen_Skylake) and then CPU_Var = ULT);</span><br><span> </span><br><span> ----- CPU pipe: --------</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Tertiary_Pipe : constant Boolean := CPU >= Ivybridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Tertiary_Pipe : constant Boolean := Ivybridge_Plus;</span><br><span> Disable_Trickle_Feed : constant Boolean := Gen /= Haswell;</span><br><span style="color: hsl(0, 100%, 40%);">- Pipe_Enabled_Workaround : constant Boolean := CPU = Broadwell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Pipe_Enabled_Workaround : constant Boolean := CPU_Broadwell;</span><br><span> Has_EDP_Transcoder : constant Boolean := Gen >= Haswell;</span><br><span style="color: hsl(0, 100%, 40%);">- Use_PDW_For_EDP_Scaling : constant Boolean := CPU = Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Use_PDW_For_EDP_Scaling : constant Boolean := CPU_Haswell;</span><br><span> Has_Pipe_DDI_Func : constant Boolean := Gen >= Haswell;</span><br><span> Has_Trans_Clk_Sel : constant Boolean := Gen >= Haswell;</span><br><span> Has_Pipe_MSA_Misc : constant Boolean := Gen >= Haswell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Pipeconf_Misc : constant Boolean := Broadwell_Plus;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Pipeconf_BPC : constant Boolean := not CPU_Haswell;</span><br><span> Has_Plane_Control : constant Boolean := Gen >= Broxton;</span><br><span> Has_DSP_Linoff : constant Boolean := Gen <= Ironlake;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge;</span><br><span style="color: hsl(0, 100%, 40%);">- VGA_Plane_Workaround : constant Boolean := CPU = Ivybridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_PF_Pipe_Select : constant Boolean := CPU_Ivybridge or CPU_Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Cursor_FBC_Control : constant Boolean := Ivybridge_Plus;</span><br><span style="color: hsl(120, 100%, 40%);">+ VGA_Plane_Workaround : constant Boolean := CPU_Ivybridge;</span><br><span> Has_GMCH_DP_Transcoder : constant Boolean := Gen = G45;</span><br><span> Has_GMCH_VGACNTRL : constant Boolean := Gen = G45;</span><br><span> Has_GMCH_PFIT_CONTROL : constant Boolean := Gen = G45;</span><br><span>@@ -76,24 +101,22 @@</span><br><span> </span><br><span> ----- PCH/FDI: ---------</span><br><span> Has_PCH : constant Boolean := Gen /= Broxton and Gen /= G45;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or</span><br><span style="color: hsl(0, 100%, 40%);">- (CPU in Haswell .. Broadwell</span><br><span style="color: hsl(0, 100%, 40%);">- and not Is_ULT);</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_PCH_DAC : constant Boolean :=</span><br><span style="color: hsl(120, 100%, 40%);">+ (Gen_Ironlake or (Gen_Haswell and then not Is_ULT));</span><br><span> </span><br><span> Has_PCH_Aux_Channels : constant Boolean := Gen in Ironlake .. Haswell;</span><br><span> </span><br><span> VGA_Has_Sync_Disable : constant Boolean := Gen <= Ironlake;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Has_Trans_Timing_Ovrrde : constant Boolean := CPU >= Sandybridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Trans_Timing_Ovrrde : constant Boolean := Sandybridge_Plus;</span><br><span> </span><br><span> Has_DPLL_SEL : constant Boolean := Gen = Ironlake;</span><br><span> Has_FDI_BPC : constant Boolean := Gen = Ironlake;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_FDI_Composite_Sel : constant Boolean := CPU = Ivybridge;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Original_ILK_Trans : constant Boolean := CPU = Ironlake;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Trans_DP_Ctl : constant Boolean := CPU in</span><br><span style="color: hsl(0, 100%, 40%);">- Sandybridge .. Ivybridge;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Ivy_Bridge_FDI : constant Boolean := CPU = Ivybridge;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_FDI_C : constant Boolean := CPU = Ivybridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_FDI_Composite_Sel : constant Boolean := CPU_Ivybridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Original_ILK_Trans : constant Boolean := CPU_Ironlake;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Trans_DP_Ctl : constant Boolean := CPU_Sandybridge or CPU_Ivybridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Ivy_Bridge_FDI : constant Boolean := CPU_Ivybridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_FDI_C : constant Boolean := CPU_Ivybridge;</span><br><span> </span><br><span> Has_FDI_RX_Power_Down : constant Boolean := Gen = Haswell;</span><br><span> </span><br><span>@@ -103,21 +126,19 @@</span><br><span> End_EDP_Training_Late : constant Boolean := Gen = Haswell;</span><br><span> Has_Per_DDI_Clock_Sel : constant Boolean := Gen = Haswell;</span><br><span> Has_HOTPLUG_CTL : constant Boolean := Gen = Haswell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_SHOTPLUG_CTL_A : constant Boolean := (CPU in Haswell .. Broadwell</span><br><span style="color: hsl(0, 100%, 40%);">- and Is_ULT) or</span><br><span style="color: hsl(0, 100%, 40%);">- CPU >= Skylake;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_SHOTPLUG_CTL_A : constant Boolean :=</span><br><span style="color: hsl(120, 100%, 40%);">+ ((Gen_Haswell and then Is_ULT) or Gen_Skylake);</span><br><span> </span><br><span> Has_DDI_PHYs : constant Boolean := Gen = Broxton;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Has_DDI_D : constant Boolean := CPU >= Haswell and</span><br><span style="color: hsl(0, 100%, 40%);">- not Is_ULT and</span><br><span style="color: hsl(0, 100%, 40%);">- not Has_DDI_PHYs;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_DDI_D : constant Boolean :=</span><br><span style="color: hsl(120, 100%, 40%);">+ ((Gen_Haswell or Gen_Skylake) and then not Is_ULT);</span><br><span> Has_DDI_E : constant Boolean := -- might be disabled by x4 eDP</span><br><span> Has_DDI_D;</span><br><span> </span><br><span> Has_DDI_Buffer_Trans : constant Boolean := Gen >= Haswell and</span><br><span> Gen /= Broxton;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Broadwell_DDI_Bufs : constant Boolean := CPU = Broadwell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Broadwell_DDI_Bufs : constant Boolean := CPU_Broadwell;</span><br><span> Has_Low_Voltage_Swing : constant Boolean := Gen >= Broxton;</span><br><span> Has_Iboost_Config : constant Boolean := Gen >= Skylake;</span><br><span> </span><br><span>@@ -129,14 +150,15 @@</span><br><span> Has_PCH_GMBUS : constant Boolean := Gen >= Ironlake;</span><br><span> </span><br><span> ----- Power: -----------</span><br><span style="color: hsl(0, 100%, 40%);">- Has_IPS : constant Boolean := (CPU = Haswell and Is_ULT) or</span><br><span style="color: hsl(0, 100%, 40%);">- CPU = Broadwell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_IPS_CTL_Mailbox : constant Boolean := CPU = Broadwell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_IPS : constant Boolean :=</span><br><span style="color: hsl(120, 100%, 40%);">+ (Gen_Haswell and then</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CPU_Haswell and Is_ULT) or CPU_Broadwell));</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_IPS_CTL_Mailbox : constant Boolean := CPU_Broadwell;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Has_Per_Pipe_SRD : constant Boolean := CPU >= Broadwell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Per_Pipe_SRD : constant Boolean := Broadwell_Plus;</span><br><span> </span><br><span> ----- GTT: -------------</span><br><span style="color: hsl(0, 100%, 40%);">- Has_64bit_GTT : constant Boolean := CPU >= Broadwell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_64bit_GTT : constant Boolean := Broadwell_Plus;</span><br><span> </span><br><span> ----------------------------------------------------------------------------</span><br><span> </span><br><span>@@ -155,54 +177,45 @@</span><br><span> type FDI_Per_Port is array (Port_Type) of Boolean;</span><br><span> Is_FDI_Port : constant FDI_Per_Port :=</span><br><span> (Disabled => False,</span><br><span style="color: hsl(0, 100%, 40%);">- Internal => Gen = Ironlake and Internal_Is_LVDS,</span><br><span style="color: hsl(0, 100%, 40%);">- DP1 .. HDMI3 => Gen = Ironlake,</span><br><span style="color: hsl(120, 100%, 40%);">+ Internal => Gen_Ironlake and Internal_Is_LVDS,</span><br><span style="color: hsl(120, 100%, 40%);">+ DP1 .. HDMI3 => Gen_Ironlake,</span><br><span> Analog => Has_PCH_DAC);</span><br><span> </span><br><span> type FDI_Lanes_Per_Port is array (GPU_Port) of DP_Lane_Count;</span><br><span> FDI_Lane_Count : constant FDI_Lanes_Per_Port :=</span><br><span> (DIGI_D => DP_Lane_Count_2,</span><br><span style="color: hsl(0, 100%, 40%);">- others => (if Gen = Ironlake then DP_Lane_Count_4 else DP_Lane_Count_2));</span><br><span style="color: hsl(120, 100%, 40%);">+ others => (if Gen_Ironlake then DP_Lane_Count_4 else DP_Lane_Count_2));</span><br><span> </span><br><span> FDI_Training : constant FDI_Training_Type :=</span><br><span style="color: hsl(0, 100%, 40%);">- (case CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when Ironlake => Simple_Training,</span><br><span style="color: hsl(0, 100%, 40%);">- when Sandybridge => Full_Training,</span><br><span style="color: hsl(0, 100%, 40%);">- when others => Auto_Training);</span><br><span style="color: hsl(120, 100%, 40%);">+ (if CPU_Ironlake then Simple_Training</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif CPU_Sandybridge then Full_Training</span><br><span style="color: hsl(120, 100%, 40%);">+ else Auto_Training);</span><br><span> </span><br><span> ----------------------------------------------------------------------------</span><br><span> </span><br><span> Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range :=</span><br><span style="color: hsl(0, 100%, 40%);">- (case CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when Haswell => 6,</span><br><span style="color: hsl(0, 100%, 40%);">- when Broadwell => 7,</span><br><span style="color: hsl(0, 100%, 40%);">- when Broxton => 8,</span><br><span style="color: hsl(0, 100%, 40%);">- when Skylake => 8,</span><br><span style="color: hsl(0, 100%, 40%);">- when others => 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ (if CPU_Haswell then 6</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif CPU_Broadwell then 7</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif Broxton_Plus then 8</span><br><span style="color: hsl(120, 100%, 40%);">+ else 0);</span><br><span> </span><br><span> ----------------------------------------------------------------------------</span><br><span> </span><br><span> Default_CDClk_Freq : constant Frequency_Type :=</span><br><span style="color: hsl(0, 100%, 40%);">- (case CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 => 320_000_000, -- unused</span><br><span style="color: hsl(0, 100%, 40%);">- when Ironlake |</span><br><span style="color: hsl(0, 100%, 40%);">- Haswell |</span><br><span style="color: hsl(0, 100%, 40%);">- Broadwell => 450_000_000,</span><br><span style="color: hsl(0, 100%, 40%);">- when Sandybridge |</span><br><span style="color: hsl(0, 100%, 40%);">- Ivybridge => 400_000_000,</span><br><span style="color: hsl(0, 100%, 40%);">- when Broxton => 288_000_000,</span><br><span style="color: hsl(0, 100%, 40%);">- when Skylake => 337_500_000);</span><br><span style="color: hsl(120, 100%, 40%);">+ (if Gen_G45 then 320_000_000 -- unused</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif CPU_Ironlake or Gen_Haswell then 450_000_000</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif CPU_Sandybridge or CPU_Ivybridge then 400_000_000</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif Gen_Broxton then 288_000_000</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif Gen_Skylake then 337_500_000</span><br><span style="color: hsl(120, 100%, 40%);">+ else Frequency_Type'First);</span><br><span> </span><br><span> Default_RawClk_Freq : constant Frequency_Type :=</span><br><span style="color: hsl(0, 100%, 40%);">- (case CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 => 100_000_000, -- unused, depends on FSB</span><br><span style="color: hsl(0, 100%, 40%);">- when Ironlake |</span><br><span style="color: hsl(0, 100%, 40%);">- Sandybridge |</span><br><span style="color: hsl(0, 100%, 40%);">- Ivybridge => 125_000_000,</span><br><span style="color: hsl(0, 100%, 40%);">- when Haswell |</span><br><span style="color: hsl(0, 100%, 40%);">- Broadwell => (if Is_ULT then 24_000_000 else 125_000_000),</span><br><span style="color: hsl(0, 100%, 40%);">- when Broxton => Frequency_Type'First, -- none needed</span><br><span style="color: hsl(0, 100%, 40%);">- when Skylake => 24_000_000);</span><br><span style="color: hsl(120, 100%, 40%);">+ (if Gen_G45 then 100_000_000 -- unused, depends on FSB</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif Gen_Ironlake then 125_000_000</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif Gen_Haswell then (if Is_ULT then 24_000_000 else 125_000_000)</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif Gen_Broxton then Frequency_Type'First -- none needed</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif Gen_Skylake then 24_000_000</span><br><span style="color: hsl(120, 100%, 40%);">+ else Frequency_Type'First);</span><br><span> </span><br><span> Raw_Clock : Frequency_Type := Default_RawClk_Freq</span><br><span> with Part_Of => GMA.Config_State;</span><br><span>@@ -215,19 +228,18 @@</span><br><span> type Width_Per_Pipe is array (Pipe_Index) of Width_Type;</span><br><span> </span><br><span> Maximum_Scalable_Width : constant Width_Per_Pipe :=</span><br><span style="color: hsl(0, 100%, 40%);">- (case CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 => -- TODO: Is this true?</span><br><span style="color: hsl(0, 100%, 40%);">- (Primary => 4096,</span><br><span style="color: hsl(0, 100%, 40%);">- Secondary => 2048,</span><br><span style="color: hsl(0, 100%, 40%);">- Tertiary => Pos32'First),</span><br><span style="color: hsl(0, 100%, 40%);">- when Ironlake..Haswell =></span><br><span style="color: hsl(0, 100%, 40%);">- (Primary => 4096,</span><br><span style="color: hsl(0, 100%, 40%);">- Secondary => 2048,</span><br><span style="color: hsl(0, 100%, 40%);">- Tertiary => 2048),</span><br><span style="color: hsl(0, 100%, 40%);">- when Broadwell..Skylake =></span><br><span style="color: hsl(0, 100%, 40%);">- (Primary => 4096,</span><br><span style="color: hsl(0, 100%, 40%);">- Secondary => 4096,</span><br><span style="color: hsl(0, 100%, 40%);">- Tertiary => 4096));</span><br><span style="color: hsl(120, 100%, 40%);">+ (if Gen_G45 then -- TODO: Is this true?</span><br><span style="color: hsl(120, 100%, 40%);">+ (Primary => 4096,</span><br><span style="color: hsl(120, 100%, 40%);">+ Secondary => 2048,</span><br><span style="color: hsl(120, 100%, 40%);">+ Tertiary => Pos32'First)</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif Gen_Ironlake or else CPU_Haswell then</span><br><span style="color: hsl(120, 100%, 40%);">+ (Primary => 4096,</span><br><span style="color: hsl(120, 100%, 40%);">+ Secondary => 2048,</span><br><span style="color: hsl(120, 100%, 40%);">+ Tertiary => 2048)</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ (Primary => 4096,</span><br><span style="color: hsl(120, 100%, 40%);">+ Secondary => 4096,</span><br><span style="color: hsl(120, 100%, 40%);">+ Tertiary => 4096));</span><br><span> </span><br><span> -- Maximum X position of hardware cursors</span><br><span> Maximum_Cursor_X : constant := (case Gen is</span><br><span>@@ -240,19 +252,17 @@</span><br><span> </span><br><span> -- FIXME: Unknown for Broxton, Linux' i915 contains a fixme too :-D</span><br><span> HDMI_Max_Clock_24bpp : constant Frequency_Type :=</span><br><span style="color: hsl(0, 100%, 40%);">- (if Gen >= Haswell then 300_000_000 else 225_000_000);</span><br><span style="color: hsl(120, 100%, 40%);">+ (if Haswell_Plus then 300_000_000 else 225_000_000);</span><br><span> </span><br><span> ----------------------------------------------------------------------------</span><br><span> </span><br><span> GTT_PTE_Size : constant := (if Has_64bit_GTT then 8 else 4);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Fence_Base : constant := (case CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 .. Ironlake => 16#0000_3000#,</span><br><span style="color: hsl(0, 100%, 40%);">- when Sandybridge .. Skylake => 16#0010_0000#);</span><br><span style="color: hsl(120, 100%, 40%);">+ Fence_Base : constant :=</span><br><span style="color: hsl(120, 100%, 40%);">+ (if not Sandybridge_Plus then 16#0000_3000# else 16#0010_0000#);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Fence_Count : constant := (case CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 .. Sandybridge => 16,</span><br><span style="color: hsl(0, 100%, 40%);">- when Ivybridge .. Skylake => 32);</span><br><span style="color: hsl(120, 100%, 40%);">+ Fence_Count : constant :=</span><br><span style="color: hsl(120, 100%, 40%);">+ (if not Ivybridge_Plus then 16 else 32);</span><br><span> </span><br><span> ----------------------------------------------------------------------------</span><br><span> </span><br><span>diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb</span><br><span>index 967ca05..17dbeae 100644</span><br><span>--- a/common/hw-gfx-gma.adb</span><br><span>+++ b/common/hw-gfx-gma.adb</span><br><span>@@ -407,18 +407,17 @@</span><br><span> Registers.Read (Registers.AUD_VID_DID, Audio_VID_DID);</span><br><span> end case;</span><br><span> Success :=</span><br><span style="color: hsl(0, 100%, 40%);">- (case Config.CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when Broxton => Audio_VID_DID = 16#8086_280a#,</span><br><span style="color: hsl(0, 100%, 40%);">- when Skylake => Audio_VID_DID = 16#8086_2809#,</span><br><span style="color: hsl(0, 100%, 40%);">- when Broadwell => Audio_VID_DID = 16#8086_2808#,</span><br><span style="color: hsl(0, 100%, 40%);">- when Haswell => Audio_VID_DID = 16#8086_2807#,</span><br><span style="color: hsl(0, 100%, 40%);">- when Ivybridge |</span><br><span style="color: hsl(0, 100%, 40%);">- Sandybridge => Audio_VID_DID = 16#8086_2806# or</span><br><span style="color: hsl(0, 100%, 40%);">- Audio_VID_DID = 16#8086_2805#,</span><br><span style="color: hsl(0, 100%, 40%);">- when Ironlake => Audio_VID_DID = 16#0000_0000#,</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 => Audio_VID_DID = 16#8086_2801# or</span><br><span style="color: hsl(0, 100%, 40%);">- Audio_VID_DID = 16#8086_2802# or</span><br><span style="color: hsl(0, 100%, 40%);">- Audio_VID_DID = 16#8086_2803#);</span><br><span style="color: hsl(120, 100%, 40%);">+ ((Config.Gen_Broxton and Audio_VID_DID = 16#8086_280a#) or</span><br><span style="color: hsl(120, 100%, 40%);">+ (Config.Gen_Skylake and Audio_VID_DID = 16#8086_2809#) or</span><br><span style="color: hsl(120, 100%, 40%);">+ (Config.CPU_Broadwell and Audio_VID_DID = 16#8086_2808#) or</span><br><span style="color: hsl(120, 100%, 40%);">+ (Config.CPU_Haswell and Audio_VID_DID = 16#8086_2807#) or</span><br><span style="color: hsl(120, 100%, 40%);">+ ((Config.CPU_Ivybridge or</span><br><span style="color: hsl(120, 100%, 40%);">+ Config.CPU_Sandybridge) and (Audio_VID_DID = 16#8086_2806# or</span><br><span style="color: hsl(120, 100%, 40%);">+ Audio_VID_DID = 16#8086_2805#)) or</span><br><span style="color: hsl(120, 100%, 40%);">+ (Config.CPU_Ironlake and Audio_VID_DID = 16#0000_0000#) or</span><br><span style="color: hsl(120, 100%, 40%);">+ (Config.Gen_G45 and (Audio_VID_DID = 16#8086_2801# or</span><br><span style="color: hsl(120, 100%, 40%);">+ Audio_VID_DID = 16#8086_2802# or</span><br><span style="color: hsl(120, 100%, 40%);">+ Audio_VID_DID = 16#8086_2803#)));</span><br><span> end Check_Platform;</span><br><span> </span><br><span> procedure Check_Platform_PCI (Success : out Boolean)</span><br><span>@@ -681,26 +680,24 @@</span><br><span> Pre => Is_Initialized</span><br><span> is</span><br><span> GGC_Reg : constant :=</span><br><span style="color: hsl(0, 100%, 40%);">- (case Config.CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 | Ironlake => 16#52#,</span><br><span style="color: hsl(0, 100%, 40%);">- when Sandybridge .. Skylake => 16#50#);</span><br><span style="color: hsl(120, 100%, 40%);">+ (if Config.Gen_G45 or Config.CPU_Ironlake then 16#52# else 16#50#);</span><br><span> GGC : Word16;</span><br><span> begin</span><br><span> Dev.Read16 (GGC, GGC_Reg);</span><br><span style="color: hsl(0, 100%, 40%);">- case Config.CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 | Ironlake =></span><br><span style="color: hsl(0, 100%, 40%);">- GTT_Size := GTT_Size_Gen4 (GGC);</span><br><span style="color: hsl(0, 100%, 40%);">- Stolen_Size := Stolen_Size_Gen4 (GGC);</span><br><span style="color: hsl(0, 100%, 40%);">- when Sandybridge .. Haswell =></span><br><span style="color: hsl(0, 100%, 40%);">- GTT_Size := GTT_Size_Gen6 (GGC);</span><br><span style="color: hsl(0, 100%, 40%);">- Stolen_Size := Stolen_Size_Gen6 (GGC);</span><br><span style="color: hsl(0, 100%, 40%);">- when Broadwell =></span><br><span style="color: hsl(0, 100%, 40%);">- GTT_Size := GTT_Size_Gen8 (GGC);</span><br><span style="color: hsl(0, 100%, 40%);">- Stolen_Size := Stolen_Size_Gen8 (GGC);</span><br><span style="color: hsl(0, 100%, 40%);">- when Broxton .. Skylake =></span><br><span style="color: hsl(0, 100%, 40%);">- GTT_Size := GTT_Size_Gen8 (GGC);</span><br><span style="color: hsl(0, 100%, 40%);">- Stolen_Size := Stolen_Size_Gen9 (GGC);</span><br><span style="color: hsl(0, 100%, 40%);">- end case;</span><br><span style="color: hsl(120, 100%, 40%);">+ if Config.Gen_G45 or Config.CPU_Ironlake then</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_Size := GTT_Size_Gen4 (GGC);</span><br><span style="color: hsl(120, 100%, 40%);">+ Stolen_Size := Stolen_Size_Gen4 (GGC);</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif Config.CPU_Sandybridge or Config.CPU_Ivybridge or Config.CPU_Haswell</span><br><span style="color: hsl(120, 100%, 40%);">+ then</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_Size := GTT_Size_Gen6 (GGC);</span><br><span style="color: hsl(120, 100%, 40%);">+ Stolen_Size := Stolen_Size_Gen6 (GGC);</span><br><span style="color: hsl(120, 100%, 40%);">+ elsif Config.CPU_Broadwell then</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_Size := GTT_Size_Gen8 (GGC);</span><br><span style="color: hsl(120, 100%, 40%);">+ Stolen_Size := Stolen_Size_Gen8 (GGC);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ GTT_Size := GTT_Size_Gen8 (GGC);</span><br><span style="color: hsl(120, 100%, 40%);">+ Stolen_Size := Stolen_Size_Gen9 (GGC);</span><br><span style="color: hsl(120, 100%, 40%);">+ end if;</span><br><span> end Decode_Stolen;</span><br><span> </span><br><span> -- Additional runtime validation that FB fits stolen memory and aperture.</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27060">change 27060</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27060"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: libgfxinit </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I307d1dd56f480fdb4fbc6e2e25fc5f413c4158f8 </div>
<div style="display:none"> Gerrit-Change-Number: 27060 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>