<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27030">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Add mtcmos init support<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=the refactored code works fine on the new platform (with the rest<br> of the patches applied) and Elm platform<br><br>Change-Id: I41f16ba36432a8bbc47793cec2979753c9f84b43<br>Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com><br>---<br>M src/soc/mediatek/mt8183/Makefile.inc<br>M src/soc/mediatek/mt8183/include/soc/addressmap.h<br>A src/soc/mediatek/mt8183/include/soc/infracfg.h<br>A src/soc/mediatek/mt8183/include/soc/mtcmos_extend.h<br>A src/soc/mediatek/mt8183/include/soc/smi.h<br>A src/soc/mediatek/mt8183/include/soc/spm.h<br>A src/soc/mediatek/mt8183/mtcmos_extend.c<br>7 files changed, 976 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/27030/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>index 9f80500..e827cd8 100644</span><br><span>--- a/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>+++ b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>@@ -1,6 +1,7 @@</span><br><span> ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y)</span><br><span> </span><br><span> bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += ../common/mtcmos.c mtcmos_extend.c</span><br><span> bootblock-$(CONFIG_SPI_FLASH) += spi.c</span><br><span> bootblock-y += ../common/timer.c</span><br><span> ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>index 59f4acf..251e7f7 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>@@ -22,8 +22,11 @@</span><br><span> };</span><br><span> </span><br><span> enum {</span><br><span style="color: hsl(0, 100%, 40%);">- GPT_BASE = IO_PHYS + 0x00008000,</span><br><span style="color: hsl(0, 100%, 40%);">- UART0_BASE = IO_PHYS + 0x01002000,</span><br><span style="color: hsl(120, 100%, 40%);">+ INFRACFG_AO_BASE = IO_PHYS + 0x00001000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPM_BASE = IO_PHYS + 0x00006000,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPT_BASE = IO_PHYS + 0x00008000,</span><br><span style="color: hsl(120, 100%, 40%);">+ UART0_BASE = IO_PHYS + 0x01002000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SMI_BASE = IO_PHYS + 0x04019000,</span><br><span> };</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/infracfg.h b/src/soc/mediatek/mt8183/include/soc/infracfg.h</span><br><span>new file mode 100644</span><br><span>index 0000000..922d977</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/infracfg.h</span><br><span>@@ -0,0 +1,291 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_MEDIATEK_MT8183_INFRACFG_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_MEDIATEK_MT8183_INFRACFG_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mt8183_infracfg_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved1[20];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_dcmctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved2[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_bus_dcm_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 peri_bus_dcm_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mem_dcm_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfs_mem_dcm_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_sw_cg_0_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_sw_cg_0_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_sw_cg_1_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_sw_cg_1_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_sw_cg_0_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_sw_cg_1_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_clk_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mem_cg_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 p2p_rx_clk_on;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_sw_cg_2_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_sw_cg_2_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_sw_cg_2_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved3[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dramc_wbr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved4[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_sw_cg_3_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_sw_cg_3_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 module_sw_cg_3_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved5[13];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 i2c_dbtool_misc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md_sleep_ctrl_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pmicw_clock_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved6[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_rst0_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_rst0_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_rst0_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved7[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_rst1_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_rst1_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_rst1_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved8[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_rst2_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_rst2_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_rst2_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved9[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_rst3_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_rst3_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_globalcon_rst3_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved10[41];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_si0_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_si1_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_mdbus_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_mci_si0_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_mci_si1_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_mci_si2_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_mci_async_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_mci_cg_mfg_sec_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_sta0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_sta1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_axi_aslice_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_apb_async_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_si2_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved11[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_mci_trans_con_read;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_mci_trans_con_write;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_mci_id_remap_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_mci_emi_trans_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_sta0_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_sta1_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved12[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_aslice_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved13[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_mi_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_cbip_aslice_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_cbip_slice_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_top_master_sideband;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved14[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_trans_limiter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_emi_gmc_l2c_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_cbip_slice_ctrl_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_mfg_slave_gals_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_mfg_master_m0_gals_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_mfg_master_m1_gals_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_top_master_sideband_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_1_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_1_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_cbip_slice_ctrl_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved15[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_mcu;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_mcu_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_mcu_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved16[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_mm;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_mm_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_mm_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved17[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_mcu_sta0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_mcu_sta1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_mm_sta0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_topaxi_protecten_mm_sta1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved18[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_bank0_map0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_bank0_map1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_bank0_map2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_bank0_map3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_bank1_map0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_bank1_map1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_bank1_map2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_bank1_map3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_bank4_map0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_bank4_map1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_bank4_map2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_bank4_map3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md2_bank0_map0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md2_bank0_map1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md2_bank0_map2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md2_bank0_map3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved19[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md2_bank4_map0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md2_bank4_map1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md2_bank4_map2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md2_bank4_map3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c2k_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c2k_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c2k_spm_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved20[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap2md_dummy;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved21[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 conn_map0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cldma_map0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 conn_map1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 conn_bus_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_dfd_map;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 conn_map2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved22[26];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 peri_cci_sideband_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mfg_cci_sideband_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved23[62];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_dbg_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_dbg_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_dbg_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_dbg_con3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md_dbg_ck_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_dbg_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved24[58];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mfg_misc_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved25[63];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_rsvd0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_rsvd1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_rsvd2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_rsvd3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved26[92];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_sbc_key0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_sbc_key1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_sbc_key2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_sbc_key3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_sbc_key4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_sbc_key5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_sbc_key6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_sbc_key7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_sbc_key_lock;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved27[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_misc_lock;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_misc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c2k_sbc_key0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c2k_sbc_key1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c2k_sbc_key2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c2k_sbc_key3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c2k_sbc_key4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c2k_sbc_key5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c2k_sbc_key6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c2k_sbc_key7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c2k_sbc_key_lock;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved28[11];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_bonding;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved29[63];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_scpsys_apb_async_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_md32_tx_apb_async_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_md32_rx_apb_async_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_cksys_apb_async_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_pmic_wrap_tx_apb_async_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved30[59];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pll_ulposc_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pll_ulposc_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved31[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pll_auxadc_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 scp_infra_irq_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 scp_infra_irq_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 scp_infra_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved32[56];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cldma_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved33[63];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg10;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg11;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg12;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg13;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg14;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg15;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg16;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg17;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg18;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg19;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg20;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg21;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg22;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infrabus_dbg23;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved34[104];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_misc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_acp;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 misc_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_misc2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mdsys_misc_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved35[27];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_sec_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_sec_cg_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_sec_cg_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_sec_rst_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_sec_rst_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_sec_rst_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved36[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_sec_cg_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_sec_rst_con3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_sec_cg_con3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved37[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 infra_ao_sec_hyp;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_globalcon_dcmctl, 0x0050);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_bus_dcm_ctrl, 0x0070);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, module_sw_cg_3_set, 0x00c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, i2c_dbtool_misc, 0x0100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_globalcon_rst0_set, 0x0120);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_topaxi_si0_ctl, 0x0200);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_mci_trans_con_read, 0x0240);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_topaxi_mi_ctrl, 0x0270);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_topaxi_protecten_mcu, 0x02c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, md1_bank0_map0, 0x0300);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, md2_bank4_map0, 0x0350);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, conn_map0, 0x0380);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, peri_cci_sideband_con, 0x0400);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_ao_dbg_con0, 0x0500);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, mfg_misc_con, 0x0600);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_rsvd0, 0x0700);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, md1_sbc_key0, 0x0880);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_bonding, 0x0900);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_ao_scpsys_apb_async_sta, 0x0a00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, pll_ulposc_con0, 0x0b00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, pll_auxadc_con0, 0x0b10);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, cldma_ctrl, 0x0c00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infrabus_dbg0, 0x0d00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_misc, 0x0f00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_ao_sec_con, 0x0f80);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_infracfg_regs, infra_ao_sec_hyp, 0x0fb0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8183_infracfg_regs *const mt8183_infracfg =</span><br><span style="color: hsl(120, 100%, 40%);">+ (void *)INFRACFG_AO_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_MEDIATEK_MT8183_INFRACFG_H */</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/mtcmos_extend.h b/src/soc/mediatek/mt8183/include/soc/mtcmos_extend.h</span><br><span>new file mode 100644</span><br><span>index 0000000..16045f5</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/mtcmos_extend.h</span><br><span>@@ -0,0 +1,20 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2015 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __SOC_MEDIATEK_MT8183_MTCMOS_EXTEND_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __SOC_MEDIATEK_MT8183_MTCMOS_EXTEND_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mtcmos_display_bus_prot(void);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __SOC_MEDIATEK_MT8183_MTCMOS_EXTEND_H__ */</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/smi.h b/src/soc/mediatek/mt8183/include/soc/smi.h</span><br><span>new file mode 100644</span><br><span>index 0000000..e9051c2</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/smi.h</span><br><span>@@ -0,0 +1,118 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_MEDIATEK_MT8183_SMI_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_MEDIATEK_MT8183_SMI_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mt8183_smi_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved1[64];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_l1len;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_l1arb0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_l1arb1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_l1arb2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_l1arb3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_l1arb4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_l1arb5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_l1arb6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_l1arb7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved2[31];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_ena;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved3[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_type;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved4[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_act_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_req_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_ostd_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_bea_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_byt_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_cp_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_dp_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_cp_max;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_mon_axi_cos_max;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved5[15];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_bus_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved6[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_wrr_reg0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_wrr_reg1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_read_fifo_th;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_m4u_th;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_fifo_th1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_fifo_th2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_preultra_mask0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_preultra_mask1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved7[46];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_dcm;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_ela;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_m1_rultra_wrr0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_m1_rultra_wrr1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_m1_wultra_wrr0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_m1_wultra_wrr1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_m2_rultra_wrr0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_m2_rultra_wrr1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_m2_wultra_wrr0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_m2_wultra_wrr1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved8[38];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_common_clamp_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_common_clamp_en_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_common_clamp_en_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved9[13];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_debug_s0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_debug_s1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_debug_s2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_debug_s3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_debug_s4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_debug_s5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_debug_s6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_debug_s7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved10[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_debug_m0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_debug_m1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved11[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_debug_misc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_dummy;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved12[46];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_hist_rec0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_hist_rec_data0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_hist_rec_data1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_hist_rec_data2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_hist_rec_data3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_hist_rec_data4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_hist_rec_data5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_hist_rec_data6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_hist_rec_data7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_hist_rec_data8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smi_hist_rec_data9;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_smi_regs, smi_l1len, 0x0100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_smi_regs, smi_mon_axi_ena, 0x01a0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_smi_regs, smi_mon_axi_act_cnt, 0x01c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_smi_regs, smi_bus_sel, 0x0220);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_smi_regs, smi_dcm, 0x0300);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_smi_regs, smi_common_clamp_en, 0x03c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_smi_regs, smi_debug_s0, 0x0400);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_smi_regs, smi_debug_m0, 0x0430);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_smi_regs, smi_debug_misc, 0x0440);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_smi_regs, smi_hist_rec0, 0x0500);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_smi_regs, smi_hist_rec_data9, 0x0528);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8183_smi_regs *const mt8183_smi = (void *)SMI_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_MEDIATEK_MT8183_SMI_H */</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h</span><br><span>new file mode 100644</span><br><span>index 0000000..c0912c8</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/spm.h</span><br><span>@@ -0,0 +1,507 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_MEDIATEK_MT8183_SPM_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_MEDIATEK_MT8183_SPM_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SPM_PROJECT_CODE = 0xb16</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DISP_SRAM_PDN_MASK = 0x1 << 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ DISP_SRAM_ACK_MASK = 0x1 << 12,</span><br><span style="color: hsl(120, 100%, 40%);">+ AUD_SRAM_PDN_MASK = 0xf << 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ AUD_SRAM_ACK_MASK = 0xf << 12,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mtk_spm_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 poweron_config_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_power_on_val0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_power_on_val1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_clk_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_clk_settle;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ap_standby_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_im_ptr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_im_len;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg_data_ini;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_pwr_io_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_timer_val;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_val;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_im_host_rw_ptr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_im_host_rw_dat;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector10;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector11;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector12;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector13;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector14;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector15;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_vector_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved1[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sram_rsv_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_swint;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_swint_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_swint_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_scp_mailbox;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 scp_spm_mailbox;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_window_len;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_idle_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_scp_irq;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_cpu_wakeup_event;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_irq_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_src_req;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_src_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_src2_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_wakeup_event_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_wakeup_event_ext_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_event_clear;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 scp_clk_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_debug_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ddr_en_dbc_len;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ahb_bus_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_src3_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ddr_en_emi_dbc_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md32_clk_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved2[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg0_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg1_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg2_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg3_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg4_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg5_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg6_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg7_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg8_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg9_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg10_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg11_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg12_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg13_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg14_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg15_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg12_mask_b_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg12_ext_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_reg12_ext_mask_b_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_event_reg_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_timer_out;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_out;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_irq_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_wakeup_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_wakeup_ext_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_wakeup_misc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 bus_protect_rdy;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 bus_protect2_rdy;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 subsys_idle_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpu_idle_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_fsm_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 src_req_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pwr_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pwr_status_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpu_pwr_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpu_pwr_status_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 misc_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_src_rdy_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved3[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dramc_dbg_latch;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_last_sta0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_last_sta1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_last_sta2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_last_sta3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_curr_sta0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_curr_sta1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_curr_sta2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_curr_sta3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_twam_timer_out;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved4[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 bus_protect3_rdy;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved5[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 src_ddren_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved6[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcu_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cputop_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu1_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu2_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu3_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cputop_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu0_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu1_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu2_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu3_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved7[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cputop_l2_pdn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cputop_l2_sleep_b;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_l1_pdn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu1_l1_pdn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu2_l1_pdn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu3_l1_pdn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cputop_l2_pdn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cputop_l2_sleep_b;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu0_l1_pdn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu1_l1_pdn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu2_l1_pdn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu3_l1_pdn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved8[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpu_ext_buck_iso;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved9[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dummy1_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 bypass_spmc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spmc_dormant_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 armpll_clk_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spmc_in_ret;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved10[15];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 vde_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ven_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 isp_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dis_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mfg_core1_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 audio_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ifr_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dpy_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md1_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 vpu_top_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved11[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 conn_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 vpu_core2_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mfg_async_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mfg_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 vpu_core0_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 vpu_core1_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cam_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mfg_2d_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mfg_core0_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sysram_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sysrom_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sspm_sram_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 scp_sram_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved12[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ufs_sram_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved13[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dummy_sram_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved14[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md_ext_buck_iso_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md_sram_iso_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md_extra_pwr_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved15[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ext_buck_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved16[11];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbist_efuse_repair_ack_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved17[11];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_mdbsi_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_mas_pause_mask_b;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_mas_pause2_mask_b;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_bsi_gen;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_bsi_en_sr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_bsi_clk_sr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_bsi_d0_sr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_bsi_d1_sr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_bsi_d2_sr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ap_sema;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_spm_sema;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_mdsrc_req;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved18[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2md_dvfs_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 md2spm_dvfs_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dramc_dpy_clk_sw_con_rsv;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dpy_lp_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpu_dvfs_req;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pll_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_emi_bw_mode;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap2md_peer_wakeup;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ulposc_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2mm_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dramc_dpy_clk_sw_con_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dramc_dpy_clk_sw_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_s1_mode_ch;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emi_self_refresh_ch_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dramc_dpy_clk_sw_con_sel2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dramc_dpy_clk_sw_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dramc_dmyrd_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_drs_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sema_m0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sema_m1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sema_m2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sema_m3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sema_m4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sema_m5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sema_m6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sema_m7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_mas_pause_mm_mask_b;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_mas_pause_mcu_mask_b;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved19[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sram_dreq_ack;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sram_dreq_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sram_dreq_con_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sram_dreq_con_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2emi_enter_ulpm;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_md32_irq;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2pmcu_int;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2pmcu_int_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2pmcu_int_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2pmcu_mailbox_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2pmcu_mailbox_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2pmcu_mailbox_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2pmcu_mailbox_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pmcu2spm_int;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pmcu2spm_int_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pmcu2spm_int_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pmcu2spm_mailbox_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pmcu2spm_mailbox_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pmcu2spm_mailbox_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pmcu2spm_mailbox_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pmcu2spm_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_irq_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu1_irq_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu2_irq_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu3_irq_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu0_irq_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu1_irq_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu2_irq_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu3_irq_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved20[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_wfi_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu1_wfi_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu2_wfi_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu3_wfi_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu0_wfi_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu1_wfi_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu2_wfi_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_cpu3_wfi_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved21[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_l2cflush;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_l2cflush;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved22[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpu_ptpod2_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved23[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 root_cputop_addr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 root_core_addr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved24[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpu_spare_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpu_spare_con_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpu_spare_con_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved25[17];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2sw_mailbox_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2sw_mailbox_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2sw_mailbox_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm2sw_mailbox_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sw2spm_int;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sw2spm_int_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sw2spm_int_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sw2spm_mailbox_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sw2spm_mailbox_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sw2spm_mailbox_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sw2spm_mailbox_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sw2spm_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_flag;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_rsv_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_rsv_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_rsv_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_rsv_sta1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pasr_dpd_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pasr_dpd_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pasr_dpd_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pasr_dpd_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_spare_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_spare_con_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_spare_con_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_10;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved26[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_18;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_sw_rsv_19;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved27[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvfsrc_event_mask_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvfsrc_event_force_on;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvfsrc_event_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_event_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_event_sta1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_level;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvfs_abort_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvfs_abort_others_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dfs_level;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvs_level;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_misc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved28[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spare_src_req_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 scp_vcore_level;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sc_mm_ck_sel_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved29[9];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spare_ack_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spare_ack_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved30[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_con1_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved31[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd10;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd11;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd12;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd13;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd14;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_dvfs_cmd15;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved32[12];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 wdt_latch_spare0_fix;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 wdt_latch_spare1_fix;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 wdt_latch_spare2_fix;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 wdt_latch_spare3_fix;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spare_ack_in_fix;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dcha_latch_rsv0_fix;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dchb_latch_rsv0_fix;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved33[25];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 wdt_latch_spare0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 wdt_latch_spare1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 wdt_latch_spare2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 wdt_latch_spare3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_10;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_11;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dcha_gating_latch_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dcha_gating_latch_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dcha_gating_latch_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dcha_gating_latch_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dcha_gating_latch_4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dcha_gating_latch_5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dcha_gating_latch_6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dcha_gating_latch_7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dchb_gating_latch_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dchb_gating_latch_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dchb_gating_latch_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dchb_gating_latch_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dchb_gating_latch_4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dchb_gating_latch_5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dchb_gating_latch_6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dchb_gating_latch_7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dcha_latch_rsv0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dchb_latch_rsv0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_12;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcm_wdt_latch_13;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved34[12];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pc_trace_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pc_trace_g0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pc_trace_g1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pc_trace_g2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pc_trace_g3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pc_trace_g4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pc_trace_g5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pc_trace_g6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_pc_trace_g7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved35[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_pc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_timer;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_sta;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_latch;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved36[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_pc2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_sel2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_timer2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_sta2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_latch2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved37[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_con3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_pc3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_sel3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_timer3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_sta3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_latch3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved38[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_con4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_pc4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_sel4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_timer4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_sta4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spm_ack_chk_latch4;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, pcm_reg0_data, 0x0100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, src_ddren_sta, 0x01e0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, mcu_pwr_con, 0x0200);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, mp0_cputop_l2_pdn, 0x0240);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, cpu_ext_buck_iso, 0x0290);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, dummy1_pwr_con, 0x02b0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, vde_pwr_con, 0x0300);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, ufs_sram_con, 0x036c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, dummy_sram_con, 0x0380);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, md_ext_buck_iso_con, 0x0390);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, mbist_efuse_repair_ack_sta, 0x03d0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, spm_dvfs_con, 0x0400);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, mp0_cpu0_wfi_en, 0x0530);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, root_cputop_addr, 0x0570);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, cpu_spare_con, 0x0580);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x05d0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, spm_sw_rsv_18, 0x067c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, dvfsrc_event_mask_con, 0x0690);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, spare_ack_sta, 0x06f0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, spm_dvfs_con1, 0x0700);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, spm_dvfs_cmd0, 0x0710);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, wdt_latch_spare0_fix, 0x0780);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, pcm_wdt_latch_0, 0x0800);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, spm_pc_trace_con, 0x08c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, spm_ack_chk_con, 0x0900);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, spm_ack_chk_con2, 0x0920);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, spm_ack_chk_con3, 0x0940);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, spm_ack_chk_con4, 0x0960);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spm_regs, spm_ack_chk_latch4, 0x0974);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_MEDIATEK_MT8183_SPM_H */</span><br><span>diff --git a/src/soc/mediatek/mt8183/mtcmos_extend.c b/src/soc/mediatek/mt8183/mtcmos_extend.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d983dcf</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/mtcmos_extend.c</span><br><span>@@ -0,0 +1,34 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/infracfg.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/mtcmos_extend.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DIS_PROT_STEP1_0_MASK = 0x3 << 16,</span><br><span style="color: hsl(120, 100%, 40%);">+ DIS_PROT_STEP2_0_MASK = 0x3 << 10,</span><br><span style="color: hsl(120, 100%, 40%);">+ DIS_PROT_STEP2_1_MASK = 0xff,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mtcmos_display_bus_prot(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_infracfg->infra_topaxi_protecten_clr,</span><br><span style="color: hsl(120, 100%, 40%);">+ DIS_PROT_STEP2_0_MASK);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_smi->smi_common_clamp_en_clr, DIS_PROT_STEP2_1_MASK);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_infracfg->infra_topaxi_protecten_1_clr,</span><br><span style="color: hsl(120, 100%, 40%);">+ DIS_PROT_STEP1_0_MASK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27030">change 27030</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27030"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I41f16ba36432a8bbc47793cec2979753c9f84b43 </div>
<div style="display:none"> Gerrit-Change-Number: 27030 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>