<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27039">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[RFC]sb/intel/acpi_pirq_gen.c: Have the southbridge provide RCBA<br><br>Instead of redefining the RCBA macros, have the southbridge provide<br>the offset.<br><br>Change-Id: I5beb7ffd460f32deaa9e0f397f444baeee9c41fb<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/southbridge/intel/bd82x6x/lpc.c<br>M src/southbridge/intel/common/acpi_pirq_gen.c<br>M src/southbridge/intel/common/acpi_pirq_gen.h<br>M src/southbridge/intel/common/rcba_pirq.c<br>M src/southbridge/intel/common/rcba_pirq.h<br>5 files changed, 11 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/27039/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>index 611b08f..10a0ffa 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>@@ -824,7 +824,7 @@</span><br><span> config_t *chip = dev->chip_info;</span><br><span> </span><br><span> intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);</span><br><span style="color: hsl(0, 100%, 40%);">- intel_acpi_gen_def_acpi_pirq(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ intel_acpi_gen_def_acpi_pirq(dev, (uint32_t *)DEFAULT_RCBA);</span><br><span> }</span><br><span> </span><br><span> static void lpc_final(struct device *dev)</span><br><span>diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c</span><br><span>index 1f1a2ab..2fbc395 100644</span><br><span>--- a/src/southbridge/intel/common/acpi_pirq_gen.c</span><br><span>+++ b/src/southbridge/intel/common/acpi_pirq_gen.c</span><br><span>@@ -27,7 +27,7 @@</span><br><span> EMIT_PICM,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int create_pirq_matrix(char matrix[32][4])</span><br><span style="color: hsl(120, 100%, 40%);">+static int create_pirq_matrix(char matrix[32][4], const uint32_t *rcba)</span><br><span> {</span><br><span> struct device *dev;</span><br><span> int num_devs = 0;</span><br><span>@@ -45,7 +45,7 @@</span><br><span> continue;</span><br><span> </span><br><span> matrix[pci_dev][int_pin - PCI_INT_A] =</span><br><span style="color: hsl(0, 100%, 40%);">- intel_common_map_pirq(dev, int_pin);</span><br><span style="color: hsl(120, 100%, 40%);">+ intel_common_map_pirq(dev, int_pin, rcba);</span><br><span> printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%d\n",</span><br><span> dev_path(dev), int_pin - PCI_INT_A,</span><br><span> matrix[pci_dev][int_pin - PCI_INT_A] - PIRQ_A);</span><br><span>@@ -84,7 +84,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void intel_acpi_gen_def_acpi_pirq(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void intel_acpi_gen_def_acpi_pirq(struct device *dev, const uint32_t *rcba)</span><br><span> {</span><br><span> const char *lpcb_path = acpi_device_path(dev);</span><br><span> char pci_int_mapping[32][4];</span><br><span>@@ -98,7 +98,7 @@</span><br><span> }</span><br><span> </span><br><span> memset(pci_int_mapping, 0, sizeof(pci_int_mapping));</span><br><span style="color: hsl(0, 100%, 40%);">- num_devs = create_pirq_matrix(pci_int_mapping);</span><br><span style="color: hsl(120, 100%, 40%);">+ num_devs = create_pirq_matrix(pci_int_mapping, rcba);</span><br><span> </span><br><span> acpigen_write_scope("\\_SB.PCI0");</span><br><span> acpigen_write_method("_PRT", 0);</span><br><span>diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h</span><br><span>index 9fdee1a..39549c0 100644</span><br><span>--- a/src/southbridge/intel/common/acpi_pirq_gen.h</span><br><span>+++ b/src/southbridge/intel/common/acpi_pirq_gen.h</span><br><span>@@ -36,8 +36,9 @@</span><br><span> PIRQ_H,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void intel_acpi_gen_def_acpi_pirq(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void intel_acpi_gen_def_acpi_pirq(struct device *dev, const uint32_t *rcba);</span><br><span> enum pirq intel_common_map_pirq(const struct device *dev,</span><br><span style="color: hsl(0, 100%, 40%);">- const enum pci_pin pci_pin);</span><br><span style="color: hsl(120, 100%, 40%);">+ const enum pci_pin pci_pin,</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint32_t *rcba);</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c</span><br><span>index 7f97971..f1e4a82 100644</span><br><span>--- a/src/southbridge/intel/common/rcba_pirq.c</span><br><span>+++ b/src/southbridge/intel/common/rcba_pirq.c</span><br><span>@@ -28,7 +28,8 @@</span><br><span> };</span><br><span> </span><br><span> enum pirq intel_common_map_pirq(const struct device *dev,</span><br><span style="color: hsl(0, 100%, 40%);">- const enum pci_pin pci_pin)</span><br><span style="color: hsl(120, 100%, 40%);">+ const enum pci_pin pci_pin,</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint32_t *rcba)</span><br><span> {</span><br><span> u8 slot = PCI_SLOT(dev->path.pci.devfn);</span><br><span> u8 shift = 4 * (pci_pin - PCI_INT_A);</span><br><span>@@ -50,7 +51,7 @@</span><br><span> </span><br><span> reg = pirq_dir_route_reg[slot - MIN_SLOT];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pirq = (RCBA16(reg) >> shift) & 0x7;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq = (read16(rcba + reg) >> shift) & 0x7;</span><br><span> </span><br><span> return (enum pirq)(PIRQ_A + pirq);</span><br><span> }</span><br><span>diff --git a/src/southbridge/intel/common/rcba_pirq.h b/src/southbridge/intel/common/rcba_pirq.h</span><br><span>index cf76fb3..e5ac409 100644</span><br><span>--- a/src/southbridge/intel/common/rcba_pirq.h</span><br><span>+++ b/src/southbridge/intel/common/rcba_pirq.h</span><br><span>@@ -37,8 +37,4 @@</span><br><span> #define D20IR 0x3160 /* 16bit */</span><br><span> #define D19IR 0x3168 /* 16bit */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x))))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27039">change 27039</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5beb7ffd460f32deaa9e0f397f444baeee9c41fb </div>
<div style="display:none"> Gerrit-Change-Number: 27039 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>