<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27037">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Use {pci,pnp}_devfn_t instead of device_t<br><br>Change-Id: I7a1a496a39b41cdf963a2e9b0042c206da52285b<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/intel/apollolake/uart.c<br>M src/soc/intel/broadwell/romstage/uart.c<br>M src/soc/intel/broadwell/smihandler.c<br>M src/soc/intel/broadwell/spi.c<br>M src/soc/intel/cannonlake/lpc.c<br>M src/soc/intel/cannonlake/uart.c<br>M src/soc/intel/common/block/smm/smihandler.c<br>M src/soc/intel/denverton_ns/bootblock/uart.c<br>M src/soc/intel/denverton_ns/memmap.c<br>M src/soc/intel/denverton_ns/romstage.c<br>M src/soc/intel/denverton_ns/smihandler.c<br>M src/soc/intel/skylake/bootblock/pch.c<br>M src/soc/intel/skylake/bootblock/report_platform.c<br>M src/soc/intel/skylake/pmc.c<br>M src/soc/intel/skylake/pmutil.c<br>15 files changed, 76 insertions(+), 25 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/27037/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c</span><br><span>index 54b280d..a59b567 100644</span><br><span>--- a/src/soc/intel/apollolake/uart.c</span><br><span>+++ b/src/soc/intel/apollolake/uart.c</span><br><span>@@ -60,7 +60,11 @@</span><br><span> void pch_uart_init(void)</span><br><span> {</span><br><span> uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> /* Get a 0-based pad index. See invalid_uart_for_console() above. */</span><br><span> const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;</span><br><span>diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c</span><br><span>index 1ea7cc2..abc4a47 100644</span><br><span>--- a/src/soc/intel/broadwell/romstage/uart.c</span><br><span>+++ b/src/soc/intel/broadwell/romstage/uart.c</span><br><span>@@ -48,7 +48,11 @@</span><br><span> {</span><br><span> /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */</span><br><span> u32 gpiodf = 0x131f;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> /* Put UART in byte access mode for 16550 compatibility */</span><br><span> switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {</span><br><span>diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c</span><br><span>index 0b8a970..24f6a3d 100644</span><br><span>--- a/src/soc/intel/broadwell/smihandler.c</span><br><span>+++ b/src/soc/intel/broadwell/smihandler.c</span><br><span>@@ -80,7 +80,11 @@</span><br><span> for (slot = 0; slot < 0x20; slot++) {</span><br><span> for (func = 0; func < 8; func++) {</span><br><span> u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> val = pci_read_config32(dev, PCI_VENDOR_ID);</span><br><span> </span><br><span>diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c</span><br><span>index 7a764f1..7d862f2 100644</span><br><span>--- a/src/soc/intel/broadwell/spi.c</span><br><span>+++ b/src/soc/intel/broadwell/spi.c</span><br><span>@@ -266,7 +266,11 @@</span><br><span> uint8_t *rcrb; /* Root Complex Register Block */</span><br><span> uint32_t rcba; /* Root Complex Base Address */</span><br><span> uint8_t bios_cntl;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_DEV_LPC;</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCH_DEV_LPC;</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = PCH_DEV_LPC;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> ich9_spi_regs *ich9_spi;</span><br><span> </span><br><span> pci_read_config_dword(dev, 0xf0, &rcba);</span><br><span>diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c</span><br><span>index 69a921f..d399d1b 100644</span><br><span>--- a/src/soc/intel/cannonlake/lpc.c</span><br><span>+++ b/src/soc/intel/cannonlake/lpc.c</span><br><span>@@ -140,8 +140,11 @@</span><br><span> pch_interrupt_routing[7] = config->pirqh_routing;</span><br><span> </span><br><span> itss_irq_init(pch_interrupt_routing);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- device_t irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {</span><br><span> u8 int_pin = 0, int_line = 0;</span><br><span> </span><br><span>diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c</span><br><span>index 6aad685..8040410 100644</span><br><span>--- a/src/soc/intel/cannonlake/uart.c</span><br><span>+++ b/src/soc/intel/cannonlake/uart.c</span><br><span>@@ -35,7 +35,11 @@</span><br><span> </span><br><span> static const struct port {</span><br><span> struct pad_config pads[2]; /* just TX and RX */</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> } uart_ports[] = {</span><br><span> {.dev = PCH_DEV_UART0,</span><br><span> .pads = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* RX */</span><br><span>diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c</span><br><span>index d8ac2f3..b49f2a3 100644</span><br><span>--- a/src/soc/intel/common/block/smm/smihandler.c</span><br><span>+++ b/src/soc/intel/common/block/smm/smihandler.c</span><br><span>@@ -134,7 +134,11 @@</span><br><span> for (slot = 0; slot < 0x20; slot++) {</span><br><span> for (func = 0; func < 8; func++) {</span><br><span> u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> if (!smihandler_soc_disable_busmaster(dev))</span><br><span> continue;</span><br><span>diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c</span><br><span>index 9af42ee..7d97661 100644</span><br><span>--- a/src/soc/intel/denverton_ns/bootblock/uart.c</span><br><span>+++ b/src/soc/intel/denverton_ns/bootblock/uart.c</span><br><span>@@ -31,8 +31,11 @@</span><br><span> u32 mmio_base)</span><br><span> {</span><br><span> register uint16_t reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- device_t uart_dev = PCI_DEV(bus, dev, func);</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t uart_dev = PCI_DEV(bus, dev, func);</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *uart_dev = PCI_DEV(bus, dev, func);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> /* We're using MMIO for HSUARTs. This section is needed for logging</span><br><span> * from FSP only</span><br><span>diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c</span><br><span>index 3fe41d2..813d5c6 100644</span><br><span>--- a/src/soc/intel/denverton_ns/memmap.c</span><br><span>+++ b/src/soc/intel/denverton_ns/memmap.c</span><br><span>@@ -30,8 +30,11 @@</span><br><span> /* Returns base of requested region encoded in the system agent. */</span><br><span> static inline uintptr_t system_agent_region_base(size_t reg)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> /* All regions concerned for have 1 MiB alignment. */</span><br><span> return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c</span><br><span>index 105298e..3da349a 100644</span><br><span>--- a/src/soc/intel/denverton_ns/romstage.c</span><br><span>+++ b/src/soc/intel/denverton_ns/romstage.c</span><br><span>@@ -50,7 +50,11 @@</span><br><span> static void early_pmc_init(void)</span><br><span> {</span><br><span> /* PMC (B0:D31:F2). */</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_PMC_DEV;</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCH_PMC_DEV;</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = PCH_PMC_DEV;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> /* Is PMC present */</span><br><span> if (pci_read_config16(dev, 0) == 0xffff) {</span><br><span>@@ -99,7 +103,11 @@</span><br><span> static void early_tco_init(void)</span><br><span> {</span><br><span> /* SMBUS (B0:D31:F4). */</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> /* Configure TCO base address */</span><br><span> if (pci_read_config16(dev, TCOBASE) == 0xffff) {</span><br><span>diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c</span><br><span>index e434c1c..d97bc24 100644</span><br><span>--- a/src/soc/intel/denverton_ns/smihandler.c</span><br><span>+++ b/src/soc/intel/denverton_ns/smihandler.c</span><br><span>@@ -65,7 +65,11 @@</span><br><span> for (slot = 0; slot < 0x20; slot++) {</span><br><span> for (func = 0; func < 8; func++) {</span><br><span> u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> val = pci_read_config32(dev, PCI_VENDOR_ID);</span><br><span> </span><br><span>diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c</span><br><span>index 521a1b7..ef61a60 100644</span><br><span>--- a/src/soc/intel/skylake/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/skylake/bootblock/pch.c</span><br><span>@@ -46,7 +46,7 @@</span><br><span> </span><br><span> static void enable_p2sbbar(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_DEV_P2SB;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCH_DEV_P2SB;</span><br><span> </span><br><span> /* Enable PCR Base address in PCH */</span><br><span> pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);</span><br><span>diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c</span><br><span>index 7473c57..8fd6599 100644</span><br><span>--- a/src/soc/intel/skylake/bootblock/report_platform.c</span><br><span>+++ b/src/soc/intel/skylake/bootblock/report_platform.c</span><br><span>@@ -104,12 +104,12 @@</span><br><span> { PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, "Kabylake DT GT2" },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static uint8_t get_dev_revision(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t get_dev_revision(pci_devfn_t dev)</span><br><span> {</span><br><span> return pci_read_config8(dev, PCI_REVISION_ID);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static uint16_t get_dev_id(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static uint16_t get_dev_id(pci_devfn_t dev)</span><br><span> {</span><br><span> return pci_read_config16(dev, PCI_DEVICE_ID);</span><br><span> }</span><br><span>@@ -171,7 +171,7 @@</span><br><span> static void report_mch_info(void)</span><br><span> {</span><br><span> int i;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = SA_DEV_ROOT;</span><br><span> uint16_t mchid = get_dev_id(dev);</span><br><span> uint8_t mch_revision = get_dev_revision(dev);</span><br><span> const char *mch_type = "Unknown";</span><br><span>@@ -190,7 +190,7 @@</span><br><span> static void report_pch_info(void)</span><br><span> {</span><br><span> int i;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_DEV_LPC;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCH_DEV_LPC;</span><br><span> uint16_t lpcid = get_dev_id(dev);</span><br><span> const char *pch_type = "Unknown";</span><br><span> </span><br><span>@@ -207,7 +207,7 @@</span><br><span> static void report_igd_info(void)</span><br><span> {</span><br><span> int i;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = SA_DEV_IGD;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = SA_DEV_IGD;</span><br><span> uint16_t igdid = get_dev_id(dev);</span><br><span> const char *igd_type = "Unknown";</span><br><span> </span><br><span>diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c</span><br><span>index ecdc6bb..a2623d9 100644</span><br><span>--- a/src/soc/intel/skylake/pmc.c</span><br><span>+++ b/src/soc/intel/skylake/pmc.c</span><br><span>@@ -31,7 +31,11 @@</span><br><span> {</span><br><span> /* Set the DISB after DRAM init */</span><br><span> u32 disb_val;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_DEV_PMC;</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCH_DEV_PMC;</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = PCH_DEV_PMC;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> disb_val = pci_read_config32(dev, GEN_PMCON_A);</span><br><span> disb_val |= DISB;</span><br><span>diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c</span><br><span>index d05c812..a3974e0 100644</span><br><span>--- a/src/soc/intel/skylake/pmutil.c</span><br><span>+++ b/src/soc/intel/skylake/pmutil.c</span><br><span>@@ -19,8 +19,6 @@</span><br><span> * and the differences between PCH variants.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define __SIMPLE_DEVICE__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span>@@ -232,7 +230,11 @@</span><br><span> u8 reg8;</span><br><span> int rtc_failed;</span><br><span> /* PMC Controller Device 0x1F, Func 02 */</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_DEV_PMC;</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCH_DEV_PMC;</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = PCH_PMC;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> reg8 = pci_read_config8(dev, GEN_PMCON_B);</span><br><span> rtc_failed = reg8 & RTC_BATTERY_DEAD;</span><br><span> if (rtc_failed) {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27037">change 27037</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27037"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7a1a496a39b41cdf963a2e9b0042c206da52285b </div>
<div style="display:none"> Gerrit-Change-Number: 27037 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>