<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27059">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">gma: Introduce Generation type<br><br>It's the subset of `CPU_Type` that we have different compilation units<br>for. Also use it in the `Config` wherever we can decide something purely<br>on the `Generation` (i.e. don't mix `Gen` and `CPU` in expressions).<br><br>Change-Id: I5061021a80cd75ee3d7996ca343e6388b22bf341<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M common/Makefile.inc<br>M common/hw-gfx-gma-config.ads.template<br>M common/hw-gfx-gma-config_helpers.adb<br>M common/hw-gfx-gma.adb<br>M common/hw-gfx-gma.ads<br>M configs/broadwell<br>M configs/broadwell_ult<br>M configs/broxton<br>M configs/g45<br>M configs/haswell<br>M configs/haswell_ult<br>M configs/ironlake<br>M configs/ivybridge_edp<br>M configs/ivybridge_lvds<br>M configs/sandybridge<br>M configs/skylake<br>M configs/skylake_ult<br>17 files changed, 67 insertions(+), 61 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/59/27059/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/common/Makefile.inc b/common/Makefile.inc</span><br><span>index 8d6634e..965d6ba 100644</span><br><span>--- a/common/Makefile.inc</span><br><span>+++ b/common/Makefile.inc</span><br><span>@@ -54,7 +54,8 @@</span><br><span> </span><br><span> $(hw-gfx-gma-config-ads): $(dir)/hw-gfx-gma-config.ads.template $(cnf)</span><br><span> printf " GENERATE $(patsubst /%,%,$(subst $(obj)/,,$@))\n"</span><br><span style="color: hsl(0, 100%, 40%);">- sed -e's/<<CPU>>/$(CONFIG_GFX_GMA_CPU)/' \</span><br><span style="color: hsl(120, 100%, 40%);">+ sed -e's/<<GEN>>/$(CONFIG_GFX_GMA_GENERATION)/' \</span><br><span style="color: hsl(120, 100%, 40%);">+ -e's/<<CPU>>/$(CONFIG_GFX_GMA_CPU)/' \</span><br><span> -e's/<<CPU_VARIANT>>/$(CONFIG_GFX_GMA_CPU_VARIANT)/' \</span><br><span> -e's/<<INTERNAL_PORT>>/$(CONFIG_GFX_GMA_INTERNAL_PORT)/' \</span><br><span> -e's/<<ANALOG_I2C_PORT>>/$(CONFIG_GFX_GMA_ANALOG_I2C_PORT)/' \</span><br><span>diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template</span><br><span>index 9c89ac2..1a0beac 100644</span><br><span>--- a/common/hw-gfx-gma-config.ads.template</span><br><span>+++ b/common/hw-gfx-gma-config.ads.template</span><br><span>@@ -17,6 +17,8 @@</span><br><span> Initializes => (Valid_Port, Raw_Clock)</span><br><span> is</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ Gen : constant Generation := <<GEN>>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> CPU : constant CPU_Type := <<CPU>>;</span><br><span> </span><br><span> CPU_Var : constant CPU_Variant := <<CPU_VARIANT>>;</span><br><span>@@ -43,50 +45,49 @@</span><br><span> Internal_Is_LVDS : constant Boolean := Internal_Display = LVDS;</span><br><span> Internal_Is_EDP : constant Boolean := Internal_Display = DP;</span><br><span> Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Presence_Straps : constant Boolean := CPU /= Broxton;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Presence_Straps : constant Boolean := Gen /= Broxton;</span><br><span> Is_ULT : constant Boolean := CPU_Var = ULT;</span><br><span> </span><br><span> ----- CPU pipe: --------</span><br><span> Has_Tertiary_Pipe : constant Boolean := CPU >= Ivybridge;</span><br><span style="color: hsl(0, 100%, 40%);">- Disable_Trickle_Feed : constant Boolean := not</span><br><span style="color: hsl(0, 100%, 40%);">- (CPU in Haswell .. Broadwell);</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable_Trickle_Feed : constant Boolean := Gen /= Haswell;</span><br><span> Pipe_Enabled_Workaround : constant Boolean := CPU = Broadwell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_EDP_Transcoder : constant Boolean := CPU >= Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_EDP_Transcoder : constant Boolean := Gen >= Haswell;</span><br><span> Use_PDW_For_EDP_Scaling : constant Boolean := CPU = Haswell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Pipe_DDI_Func : constant Boolean := CPU >= Haswell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Trans_Clk_Sel : constant Boolean := CPU >= Haswell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Pipe_DDI_Func : constant Boolean := Gen >= Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Trans_Clk_Sel : constant Boolean := Gen >= Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Pipe_MSA_Misc : constant Boolean := Gen >= Haswell;</span><br><span> Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell;</span><br><span> Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Plane_Control : constant Boolean := CPU >= Broxton;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Plane_Control : constant Boolean := Gen >= Broxton;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_DSP_Linoff : constant Boolean := Gen <= Ironlake;</span><br><span> Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell;</span><br><span> Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge;</span><br><span> VGA_Plane_Workaround : constant Boolean := CPU = Ivybridge;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_GMCH_DP_Transcoder : constant Boolean := CPU = G45;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_GMCH_VGACNTRL : constant Boolean := CPU = G45;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_GMCH_PFIT_CONTROL : constant Boolean := CPU = G45;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_GMCH_DP_Transcoder : constant Boolean := Gen = G45;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_GMCH_VGACNTRL : constant Boolean := Gen = G45;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_GMCH_PFIT_CONTROL : constant Boolean := Gen = G45;</span><br><span> </span><br><span> ----- Panel power: -----</span><br><span style="color: hsl(0, 100%, 40%);">- Has_PP_Write_Protection : constant Boolean := CPU <= Ivybridge;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_PP_Port_Select : constant Boolean := CPU <= Ivybridge;</span><br><span style="color: hsl(0, 100%, 40%);">- Use_PP_VDD_Override : constant Boolean := CPU <= Ivybridge;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_PCH_Panel_Power : constant Boolean := CPU >= Ironlake;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_PP_Write_Protection : constant Boolean := Gen <= Ironlake;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_PP_Port_Select : constant Boolean := Gen <= Ironlake;</span><br><span style="color: hsl(120, 100%, 40%);">+ Use_PP_VDD_Override : constant Boolean := Gen <= Ironlake;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_PCH_Panel_Power : constant Boolean := Gen >= Ironlake;</span><br><span> </span><br><span> ----- PCH/FDI: ---------</span><br><span style="color: hsl(0, 100%, 40%);">- Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_PCH : constant Boolean := Gen /= Broxton and Gen /= G45;</span><br><span> Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or</span><br><span> (CPU in Haswell .. Broadwell</span><br><span> and not Is_ULT);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Has_PCH_Aux_Channels : constant Boolean := CPU in Ironlake .. Broadwell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_PCH_Aux_Channels : constant Boolean := Gen in Ironlake .. Haswell;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- VGA_Has_Sync_Disable : constant Boolean := CPU <= Ivybridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ VGA_Has_Sync_Disable : constant Boolean := Gen <= Ironlake;</span><br><span> </span><br><span> Has_Trans_Timing_Ovrrde : constant Boolean := CPU >= Sandybridge;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Has_DPLL_SEL : constant Boolean := CPU in Ironlake .. Ivybridge;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_FDI_BPC : constant Boolean := CPU in Ironlake .. Ivybridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_DPLL_SEL : constant Boolean := Gen = Ironlake;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_FDI_BPC : constant Boolean := Gen = Ironlake;</span><br><span> Has_FDI_Composite_Sel : constant Boolean := CPU = Ivybridge;</span><br><span> Has_Original_ILK_Trans : constant Boolean := CPU = Ironlake;</span><br><span> Has_Trans_DP_Ctl : constant Boolean := CPU in</span><br><span>@@ -94,19 +95,19 @@</span><br><span> Has_Ivy_Bridge_FDI : constant Boolean := CPU = Ivybridge;</span><br><span> Has_FDI_C : constant Boolean := CPU = Ivybridge;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Has_FDI_RX_Power_Down : constant Boolean := CPU in Haswell .. Broadwell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_FDI_RX_Power_Down : constant Boolean := Gen = Haswell;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Has_GMCH_RawClk : constant Boolean := CPU = G45;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_GMCH_RawClk : constant Boolean := Gen = G45;</span><br><span> </span><br><span> ----- DDI: -------------</span><br><span style="color: hsl(0, 100%, 40%);">- End_EDP_Training_Late : constant Boolean := CPU in Haswell .. Broadwell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Per_DDI_Clock_Sel : constant Boolean := CPU in Haswell .. Broadwell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_HOTPLUG_CTL : constant Boolean := CPU in Haswell .. Broadwell;</span><br><span style="color: hsl(120, 100%, 40%);">+ End_EDP_Training_Late : constant Boolean := Gen = Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Per_DDI_Clock_Sel : constant Boolean := Gen = Haswell;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_HOTPLUG_CTL : constant Boolean := Gen = Haswell;</span><br><span> Has_SHOTPLUG_CTL_A : constant Boolean := (CPU in Haswell .. Broadwell</span><br><span> and Is_ULT) or</span><br><span> CPU >= Skylake;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Has_DDI_PHYs : constant Boolean := CPU = Broxton;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_DDI_PHYs : constant Boolean := Gen = Broxton;</span><br><span> </span><br><span> Has_DDI_D : constant Boolean := CPU >= Haswell and</span><br><span> not Is_ULT and</span><br><span>@@ -114,18 +115,18 @@</span><br><span> Has_DDI_E : constant Boolean := -- might be disabled by x4 eDP</span><br><span> Has_DDI_D;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and</span><br><span style="color: hsl(0, 100%, 40%);">- CPU /= Broxton;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_DDI_Buffer_Trans : constant Boolean := Gen >= Haswell and</span><br><span style="color: hsl(120, 100%, 40%);">+ Gen /= Broxton;</span><br><span> Has_Broadwell_DDI_Bufs : constant Boolean := CPU = Broadwell;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_Iboost_Config : constant Boolean := CPU >= Skylake;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Low_Voltage_Swing : constant Boolean := Gen >= Broxton;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_Iboost_Config : constant Boolean := Gen >= Skylake;</span><br><span> </span><br><span> Need_DP_Aux_Mutex : constant Boolean := False; -- Skylake & (PSR | GTC)</span><br><span> </span><br><span> ----- GMBUS: -----------</span><br><span style="color: hsl(0, 100%, 40%);">- Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake;</span><br><span style="color: hsl(0, 100%, 40%);">- GMBUS_Alternative_Pins : constant Boolean := CPU = Broxton;</span><br><span style="color: hsl(0, 100%, 40%);">- Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake;</span><br><span style="color: hsl(120, 100%, 40%);">+ Ungate_GMBUS_Unit_Level : constant Boolean := Gen >= Skylake;</span><br><span style="color: hsl(120, 100%, 40%);">+ GMBUS_Alternative_Pins : constant Boolean := Gen = Broxton;</span><br><span style="color: hsl(120, 100%, 40%);">+ Has_PCH_GMBUS : constant Boolean := Gen >= Ironlake;</span><br><span> </span><br><span> ----- Power: -----------</span><br><span> Has_IPS : constant Boolean := (CPU = Haswell and Is_ULT) or</span><br><span>@@ -153,24 +154,15 @@</span><br><span> </span><br><span> type FDI_Per_Port is array (Port_Type) of Boolean;</span><br><span> Is_FDI_Port : constant FDI_Per_Port :=</span><br><span style="color: hsl(0, 100%, 40%);">- (case CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when Ironlake .. Ivybridge => FDI_Per_Port'</span><br><span style="color: hsl(0, 100%, 40%);">- (Internal => Internal_Is_LVDS,</span><br><span style="color: hsl(0, 100%, 40%);">- others => True),</span><br><span style="color: hsl(0, 100%, 40%);">- when Haswell .. Broadwell => FDI_Per_Port'</span><br><span style="color: hsl(0, 100%, 40%);">- (Analog => Has_PCH_DAC,</span><br><span style="color: hsl(0, 100%, 40%);">- others => False),</span><br><span style="color: hsl(0, 100%, 40%);">- when others => FDI_Per_Port'</span><br><span style="color: hsl(0, 100%, 40%);">- (others => False));</span><br><span style="color: hsl(120, 100%, 40%);">+ (Disabled => False,</span><br><span style="color: hsl(120, 100%, 40%);">+ Internal => Gen = Ironlake and Internal_Is_LVDS,</span><br><span style="color: hsl(120, 100%, 40%);">+ DP1 .. HDMI3 => Gen = Ironlake,</span><br><span style="color: hsl(120, 100%, 40%);">+ Analog => Has_PCH_DAC);</span><br><span> </span><br><span> type FDI_Lanes_Per_Port is array (GPU_Port) of DP_Lane_Count;</span><br><span> FDI_Lane_Count : constant FDI_Lanes_Per_Port :=</span><br><span> (DIGI_D => DP_Lane_Count_2,</span><br><span style="color: hsl(0, 100%, 40%);">- others =></span><br><span style="color: hsl(0, 100%, 40%);">- (if CPU in Ironlake .. Ivybridge then</span><br><span style="color: hsl(0, 100%, 40%);">- DP_Lane_Count_4</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- DP_Lane_Count_2));</span><br><span style="color: hsl(120, 100%, 40%);">+ others => (if Gen = Ironlake then DP_Lane_Count_4 else DP_Lane_Count_2));</span><br><span> </span><br><span> FDI_Training : constant FDI_Training_Type :=</span><br><span> (case CPU is</span><br><span>@@ -238,8 +230,8 @@</span><br><span> Tertiary => 4096));</span><br><span> </span><br><span> -- Maximum X position of hardware cursors</span><br><span style="color: hsl(0, 100%, 40%);">- Maximum_Cursor_X : constant := (case CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 .. Ivybridge => 4095,</span><br><span style="color: hsl(120, 100%, 40%);">+ Maximum_Cursor_X : constant := (case Gen is</span><br><span style="color: hsl(120, 100%, 40%);">+ when G45 .. Ironlake => 4095,</span><br><span> when Haswell .. Skylake => 8191);</span><br><span> </span><br><span> Maximum_Cursor_Y : constant := 4095;</span><br><span>@@ -248,7 +240,7 @@</span><br><span> </span><br><span> -- FIXME: Unknown for Broxton, Linux' i915 contains a fixme too :-D</span><br><span> HDMI_Max_Clock_24bpp : constant Frequency_Type :=</span><br><span style="color: hsl(0, 100%, 40%);">- (if CPU >= Haswell then 300_000_000 else 225_000_000);</span><br><span style="color: hsl(120, 100%, 40%);">+ (if Gen >= Haswell then 300_000_000 else 225_000_000);</span><br><span> </span><br><span> ----------------------------------------------------------------------------</span><br><span> </span><br><span>diff --git a/common/hw-gfx-gma-config_helpers.adb b/common/hw-gfx-gma-config_helpers.adb</span><br><span>index 57163a6..c95bebc 100644</span><br><span>--- a/common/hw-gfx-gma-config_helpers.adb</span><br><span>+++ b/common/hw-gfx-gma-config_helpers.adb</span><br><span>@@ -29,24 +29,23 @@</span><br><span> is</span><br><span> begin</span><br><span> return</span><br><span style="color: hsl(0, 100%, 40%);">- (case Config.CPU is</span><br><span style="color: hsl(0, 100%, 40%);">- when G45 =></span><br><span style="color: hsl(120, 100%, 40%);">+ (case Config.Gen is</span><br><span style="color: hsl(120, 100%, 40%);">+ when G45 => -- everything on GMCH</span><br><span> (case Port is</span><br><span> when Internal => LVDS,</span><br><span> when HDMI1 | DP1 => DIGI_B,</span><br><span> when HDMI2 | DP2 => DIGI_C,</span><br><span> when HDMI3 | DP3 => DIGI_D,</span><br><span> when Analog => VGA),</span><br><span style="color: hsl(0, 100%, 40%);">- when Ironlake .. Ivybridge => -- everything but eDP through FDI/PCH</span><br><span style="color: hsl(120, 100%, 40%);">+ when Ironlake => -- everything but eDP through FDI/PCH</span><br><span> (if Config.Internal_Is_EDP and then Port = Internal then</span><br><span> DIGI_A</span><br><span> else</span><br><span style="color: hsl(0, 100%, 40%);">- (case Pipe is</span><br><span style="color: hsl(0, 100%, 40%);">- -- FDIs are fixed to the CPU pipe</span><br><span style="color: hsl(120, 100%, 40%);">+ (case Pipe is -- FDIs are fixed to the CPU pipe</span><br><span> when Primary => DIGI_B,</span><br><span> when Secondary => DIGI_C,</span><br><span> when Tertiary => DIGI_D)),</span><br><span style="color: hsl(0, 100%, 40%);">- when Haswell .. Skylake => -- everything but VGA directly on CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ when others => -- everything but VGA directly on CPU</span><br><span> (case Port is</span><br><span> when Internal => DIGI_A, -- LVDS not available</span><br><span> when HDMI1 | DP1 => DIGI_B,</span><br><span>diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb</span><br><span>index 48b211e..967ca05 100644</span><br><span>--- a/common/hw-gfx-gma.adb</span><br><span>+++ b/common/hw-gfx-gma.adb</span><br><span>@@ -398,13 +398,13 @@</span><br><span> is</span><br><span> Audio_VID_DID : Word32;</span><br><span> begin</span><br><span style="color: hsl(0, 100%, 40%);">- case Config.CPU is</span><br><span style="color: hsl(120, 100%, 40%);">+ case Config.Gen is</span><br><span> when G45 =></span><br><span> Registers.Read (Registers.G4X_AUD_VID_DID, Audio_VID_DID);</span><br><span style="color: hsl(120, 100%, 40%);">+ when Ironlake =></span><br><span style="color: hsl(120, 100%, 40%);">+ Registers.Read (Registers.PCH_AUD_VID_DID, Audio_VID_DID);</span><br><span> when Haswell .. Skylake =></span><br><span> Registers.Read (Registers.AUD_VID_DID, Audio_VID_DID);</span><br><span style="color: hsl(0, 100%, 40%);">- when Ironlake .. Ivybridge =></span><br><span style="color: hsl(0, 100%, 40%);">- Registers.Read (Registers.PCH_AUD_VID_DID, Audio_VID_DID);</span><br><span> end case;</span><br><span> Success :=</span><br><span> (case Config.CPU is</span><br><span>diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads</span><br><span>index dcb3975..db7f2bf 100644</span><br><span>--- a/common/hw-gfx-gma.ads</span><br><span>+++ b/common/hw-gfx-gma.ads</span><br><span>@@ -35,6 +35,8 @@</span><br><span> subtype GTT_Range is Natural range 0 .. 16#8_0000# - 1;</span><br><span> GTT_Rotation_Offset : constant GTT_Range := GTT_Range'Last / 2 + 1;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ type Generation is (G45, Ironlake, Haswell, Broxton, Skylake);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> type CPU_Type is</span><br><span> (G45,</span><br><span> Ironlake,</span><br><span>diff --git a/configs/broadwell b/configs/broadwell</span><br><span>index a8aa58a..06a6c2a 100644</span><br><span>--- a/configs/broadwell</span><br><span>+++ b/configs/broadwell</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+CONFIG_GFX_GMA_GENERATION = Haswell</span><br><span> CONFIG_GFX_GMA_CPU = Broadwell</span><br><span> CONFIG_GFX_GMA_CPU_VARIANT = Normal</span><br><span> CONFIG_GFX_GMA_INTERNAL_PORT = DP</span><br><span>diff --git a/configs/broadwell_ult b/configs/broadwell_ult</span><br><span>index 3507a41..105992a 100644</span><br><span>--- a/configs/broadwell_ult</span><br><span>+++ b/configs/broadwell_ult</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+CONFIG_GFX_GMA_GENERATION = Haswell</span><br><span> CONFIG_GFX_GMA_CPU = Broadwell</span><br><span> CONFIG_GFX_GMA_CPU_VARIANT = ULT</span><br><span> CONFIG_GFX_GMA_INTERNAL_PORT = DP</span><br><span>diff --git a/configs/broxton b/configs/broxton</span><br><span>index b5f1f9a..35db833 100644</span><br><span>--- a/configs/broxton</span><br><span>+++ b/configs/broxton</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+CONFIG_GFX_GMA_GENERATION = Broxton</span><br><span> CONFIG_GFX_GMA_CPU = Broxton</span><br><span> CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A</span><br><span> CONFIG_GFX_GMA_INTERNAL_PORT = DP</span><br><span>diff --git a/configs/g45 b/configs/g45</span><br><span>index 6b54563..ef97850 100644</span><br><span>--- a/configs/g45</span><br><span>+++ b/configs/g45</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+CONFIG_GFX_GMA_GENERATION = G45</span><br><span> CONFIG_GFX_GMA_CPU = G45</span><br><span> CONFIG_GFX_GMA_CPU_VARIANT = Normal</span><br><span> CONFIG_GFX_GMA_INTERNAL_PORT = LVDS</span><br><span>diff --git a/configs/haswell b/configs/haswell</span><br><span>index d28168c..8c025da 100644</span><br><span>--- a/configs/haswell</span><br><span>+++ b/configs/haswell</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+CONFIG_GFX_GMA_GENERATION = Haswell</span><br><span> CONFIG_GFX_GMA_CPU = Haswell</span><br><span> CONFIG_GFX_GMA_CPU_VARIANT = Normal</span><br><span> CONFIG_GFX_GMA_INTERNAL_PORT = DP</span><br><span>diff --git a/configs/haswell_ult b/configs/haswell_ult</span><br><span>index 3ba633a..9559042 100644</span><br><span>--- a/configs/haswell_ult</span><br><span>+++ b/configs/haswell_ult</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+CONFIG_GFX_GMA_GENERATION = Haswell</span><br><span> CONFIG_GFX_GMA_CPU = Haswell</span><br><span> CONFIG_GFX_GMA_CPU_VARIANT = ULT</span><br><span> CONFIG_GFX_GMA_INTERNAL_PORT = DP</span><br><span>diff --git a/configs/ironlake b/configs/ironlake</span><br><span>index d29d71c..2c26a79 100644</span><br><span>--- a/configs/ironlake</span><br><span>+++ b/configs/ironlake</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+CONFIG_GFX_GMA_GENERATION = Ironlake</span><br><span> CONFIG_GFX_GMA_CPU = Ironlake</span><br><span> CONFIG_GFX_GMA_CPU_VARIANT = Normal</span><br><span> CONFIG_GFX_GMA_INTERNAL_PORT = LVDS</span><br><span>diff --git a/configs/ivybridge_edp b/configs/ivybridge_edp</span><br><span>index 257b59c..6ce8543 100644</span><br><span>--- a/configs/ivybridge_edp</span><br><span>+++ b/configs/ivybridge_edp</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+CONFIG_GFX_GMA_GENERATION = Ironlake</span><br><span> CONFIG_GFX_GMA_CPU = Ivybridge</span><br><span> CONFIG_GFX_GMA_CPU_VARIANT = Normal</span><br><span> CONFIG_GFX_GMA_INTERNAL_PORT = DP</span><br><span>diff --git a/configs/ivybridge_lvds b/configs/ivybridge_lvds</span><br><span>index 4327652..31813f9 100644</span><br><span>--- a/configs/ivybridge_lvds</span><br><span>+++ b/configs/ivybridge_lvds</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+CONFIG_GFX_GMA_GENERATION = Ironlake</span><br><span> CONFIG_GFX_GMA_CPU = Ivybridge</span><br><span> CONFIG_GFX_GMA_CPU_VARIANT = Normal</span><br><span> CONFIG_GFX_GMA_INTERNAL_PORT = LVDS</span><br><span>diff --git a/configs/sandybridge b/configs/sandybridge</span><br><span>index 2bdce64..5cc15cd 100644</span><br><span>--- a/configs/sandybridge</span><br><span>+++ b/configs/sandybridge</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+CONFIG_GFX_GMA_GENERATION = Ironlake</span><br><span> CONFIG_GFX_GMA_CPU = Sandybridge</span><br><span> CONFIG_GFX_GMA_CPU_VARIANT = Normal</span><br><span> CONFIG_GFX_GMA_INTERNAL_PORT = LVDS</span><br><span>diff --git a/configs/skylake b/configs/skylake</span><br><span>index 12ca514..26c9896 100644</span><br><span>--- a/configs/skylake</span><br><span>+++ b/configs/skylake</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+CONFIG_GFX_GMA_GENERATION = Skylake</span><br><span> CONFIG_GFX_GMA_CPU = Skylake</span><br><span> CONFIG_GFX_GMA_CPU_VARIANT = Normal</span><br><span> CONFIG_GFX_GMA_INTERNAL_PORT = DP</span><br><span>diff --git a/configs/skylake_ult b/configs/skylake_ult</span><br><span>index 94d1161..c683251 100644</span><br><span>--- a/configs/skylake_ult</span><br><span>+++ b/configs/skylake_ult</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+CONFIG_GFX_GMA_GENERATION = Skylake</span><br><span> CONFIG_GFX_GMA_CPU = Skylake</span><br><span> CONFIG_GFX_GMA_CPU_VARIANT = ULT</span><br><span> CONFIG_GFX_GMA_INTERNAL_PORT = DP</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27059">change 27059</a>. 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<div style="display:none"> Gerrit-Project: libgfxinit </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5061021a80cd75ee3d7996ca343e6388b22bf341 </div>
<div style="display:none"> Gerrit-Change-Number: 27059 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>