<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27016">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/gm45: Depreciate native graphic init<br><br>Libgfxinit provides a better alternative to the native C init. While<br>libgfxinit mandates an ada compiler, we want to encourage use of it<br>since it is in much better shape and is actually maintained.<br><br>This way libgfxinit also gets build-tested by Jenkins.<br><br>Change-Id: I540cf08cef6ff7825694ebfa36e2e6437916e657<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/lenovo/t400/Kconfig<br>M src/mainboard/lenovo/x200/Kconfig<br>M src/northbridge/intel/gm45/Kconfig<br>M src/northbridge/intel/gm45/gma.c<br>4 files changed, 4 insertions(+), 580 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/27016/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig</span><br><span>index 2b37857..e6b55a8 100644</span><br><span>--- a/src/mainboard/lenovo/t400/Kconfig</span><br><span>+++ b/src/mainboard/lenovo/t400/Kconfig</span><br><span>@@ -17,7 +17,6 @@</span><br><span> select HAVE_OPTION_TABLE</span><br><span> select HAVE_CMOS_DEFAULT</span><br><span> select HAVE_ACPI_RESUME</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_NATIVE_VGA_INIT</span><br><span> select INTEL_INT15</span><br><span> select SUPERIO_NSC_PC87382</span><br><span> select SUPERIO_NSC_PC87384</span><br><span>diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig</span><br><span>index 51a08e8..543d69c 100644</span><br><span>--- a/src/mainboard/lenovo/x200/Kconfig</span><br><span>+++ b/src/mainboard/lenovo/x200/Kconfig</span><br><span>@@ -17,7 +17,6 @@</span><br><span> select HAVE_OPTION_TABLE</span><br><span> select HAVE_CMOS_DEFAULT</span><br><span> select HAVE_ACPI_RESUME</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_NATIVE_VGA_INIT</span><br><span> select INTEL_INT15</span><br><span> select SUPERIO_NSC_PC87382</span><br><span> select DRIVERS_LENOVO_WACOM</span><br><span>diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig</span><br><span>index a45e841..da67882 100644</span><br><span>--- a/src/northbridge/intel/gm45/Kconfig</span><br><span>+++ b/src/northbridge/intel/gm45/Kconfig</span><br><span>@@ -26,8 +26,6 @@</span><br><span> select INTEL_EDID</span><br><span> select INTEL_GMA_ACPI</span><br><span> select INTEL_GMA_SSC_ALTERNATE_REF</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span> select POSTCAR_STAGE</span><br><span> select POSTCAR_CONSOLE</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c</span><br><span>index 606170c..6381919 100644</span><br><span>--- a/src/northbridge/intel/gm45/gma.c</span><br><span>+++ b/src/northbridge/intel/gm45/gma.c</span><br><span>@@ -64,579 +64,6 @@</span><br><span> gnvs_ptr->aslb = aslb;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,</span><br><span style="color: hsl(0, 100%, 40%);">- u8 *mmio, u32 physbase, u16 piobase, u32 lfb,</span><br><span style="color: hsl(0, 100%, 40%);">- struct edid *edid)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- struct edid_mode *mode;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 hactive, vactive, right_border, bottom_border;</span><br><span style="color: hsl(0, 100%, 40%);">- int hpolarity, vpolarity;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 smallest_err = 0xffffffff;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 target_frequency;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_p1 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_n = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_m1 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_m2 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_p2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0x18, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup GTT. */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 0x2000; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- outl((i << 2) | 1, piobase);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(physbase + (i << 12) + 1, piobase + 4);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + ADPA, 0x40008c18);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x7041c, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + _DPLL_B_MD, 0x3);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- vga_misc_write(0x67);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xff</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">- vga_cr_write(0x11, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i <= 0x18; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- vga_cr_write(i, cr[i]);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable screen memory to prevent garbage from appearing. */</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(1, vga_sr_read(1) | 0x20);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mode = &edid->mode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- hactive = edid->x_resolution;</span><br><span style="color: hsl(0, 100%, 40%);">- vactive = edid->y_resolution;</span><br><span style="color: hsl(0, 100%, 40%);">- right_border = mode->hborder;</span><br><span style="color: hsl(0, 100%, 40%);">- bottom_border = mode->vborder;</span><br><span style="color: hsl(0, 100%, 40%);">- hpolarity = (mode->phsync == '-');</span><br><span style="color: hsl(0, 100%, 40%);">- vpolarity = (mode->pvsync == '-');</span><br><span style="color: hsl(0, 100%, 40%);">- vsync = mode->vspw;</span><br><span style="color: hsl(0, 100%, 40%);">- hsync = mode->hspw;</span><br><span style="color: hsl(0, 100%, 40%);">- vblank = mode->vbl;</span><br><span style="color: hsl(0, 100%, 40%);">- hblank = mode->hbl;</span><br><span style="color: hsl(0, 100%, 40%);">- hfront_porch = mode->hso;</span><br><span style="color: hsl(0, 100%, 40%);">- vfront_porch = mode->vso;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(1, 1);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(0x2, 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(0x3, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(0x4, 0xe);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(1, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(2, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(3, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(4, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(5, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(6, 0x5);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(7, 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0x10, 0x1);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0x11, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- edid->bytes_per_line = (edid->bytes_per_line + 63) & ~63;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPADDR(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPSTRIDE(0), edid->bytes_per_line);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPSURF(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 0x100; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- vga_textmode_init();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- target_frequency = mode->pixel_clock;</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * p2 divisor must 7 for dual channel LVDS</span><br><span style="color: hsl(0, 100%, 40%);">- * and 14 for single channel LVDS</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_p2 = mode->lvds_dual_channel ? 7 : 14;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Find suitable divisors, m1, m2, p1, n.</span><br><span style="color: hsl(0, 100%, 40%);">- * refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2</span><br><span style="color: hsl(0, 100%, 40%);">- * should be closest to target frequency as possible</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- u32 candn, candm1, candm2, candp1;</span><br><span style="color: hsl(0, 100%, 40%);">- for (candn = 1; candn <= 3; candn++) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (candm1 = 23; candm1 >= 17; candm1--) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (candm2 = 11; candm2 >= 5; candm2--) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (candp1 = mode->lvds_dual_channel ? 6 : 8;</span><br><span style="color: hsl(0, 100%, 40%);">- candp1 >= 2; candp1--) {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 m = 5 * (candm1 + 2) + (candm2 + 2);</span><br><span style="color: hsl(0, 100%, 40%);">- u32 p = candp1 * pixel_p2;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2);</span><br><span style="color: hsl(0, 100%, 40%);">- u32 dot = DIV_ROUND_CLOSEST(vco, p);</span><br><span style="color: hsl(0, 100%, 40%);">- u32 this_err = MAX(dot, target_frequency) -</span><br><span style="color: hsl(0, 100%, 40%);">- MIN(dot, target_frequency);</span><br><span style="color: hsl(0, 100%, 40%);">- if (this_err < smallest_err) {</span><br><span style="color: hsl(0, 100%, 40%);">- smallest_err = this_err;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_n = candn;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_m1 = candm1;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_m2 = candm2;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_p1 = candp1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (smallest_err == 0xffffffff) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hactive, vactive);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Borders %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- right_border, bottom_border);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Blank %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hblank, vblank);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Sync %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hsync, vsync);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Front porch %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hfront_porch, vfront_porch);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock</span><br><span style="color: hsl(0, 100%, 40%);">- ? "Spread spectrum clock\n" : "DREF clock\n"));</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG,</span><br><span style="color: hsl(0, 100%, 40%);">- mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Polarities %d, %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hpolarity, vpolarity);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_n, pixel_m1, pixel_m2, pixel_p1);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Pixel clock %d kHz\n",</span><br><span style="color: hsl(0, 100%, 40%);">- BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /</span><br><span style="color: hsl(0, 100%, 40%);">- (pixel_n + 2) / (pixel_p1 * pixel_p2));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + LVDS,</span><br><span style="color: hsl(0, 100%, 40%);">- (hpolarity << 20) | (vpolarity << 21)</span><br><span style="color: hsl(0, 100%, 40%);">- | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_ENABLE_DITHER</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_CLOCK_A_POWERUP_ALL</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_PIPE(0));</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS</span><br><span style="color: hsl(0, 100%, 40%);">- | (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + FP0(0),</span><br><span style="color: hsl(0, 100%, 40%);">- (pixel_n << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (pixel_m1 << 8) | (pixel_m2));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DPLL(0),</span><br><span style="color: hsl(0, 100%, 40%);">- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS</span><br><span style="color: hsl(0, 100%, 40%);">- | DPLL_VGA_MODE_DIS</span><br><span style="color: hsl(0, 100%, 40%);">- | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7</span><br><span style="color: hsl(0, 100%, 40%);">- : DPLLB_LVDS_P2_CLOCK_DIV_14)</span><br><span style="color: hsl(0, 100%, 40%);">- | (0x10000 << (pixel_p1 - 1))</span><br><span style="color: hsl(0, 100%, 40%);">- | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)</span><br><span style="color: hsl(0, 100%, 40%);">- | (6 << PLL_LOAD_PULSE_PHASE_SHIFT));</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DPLL(0),</span><br><span style="color: hsl(0, 100%, 40%);">- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS</span><br><span style="color: hsl(0, 100%, 40%);">- | DPLL_VGA_MODE_DIS</span><br><span style="color: hsl(0, 100%, 40%);">- | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7</span><br><span style="color: hsl(0, 100%, 40%);">- : DPLLB_LVDS_P2_CLOCK_DIV_14)</span><br><span style="color: hsl(0, 100%, 40%);">- | (0x10000 << (pixel_p1 - 1))</span><br><span style="color: hsl(0, 100%, 40%);">- | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)</span><br><span style="color: hsl(0, 100%, 40%);">- | (6 << PLL_LOAD_PULSE_PHASE_SHIFT));</span><br><span style="color: hsl(0, 100%, 40%);">- /* Re-lock the registers. */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PP_CONTROL,</span><br><span style="color: hsl(0, 100%, 40%);">- (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + LVDS,</span><br><span style="color: hsl(0, 100%, 40%);">- (hpolarity << 20) | (vpolarity << 21)</span><br><span style="color: hsl(0, 100%, 40%);">- | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_CLOCK_A_POWERUP_ALL</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_ENABLE_DITHER</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_PIPE(0));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + HTOTAL(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + HBLANK(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive + right_border - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + HSYNC(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hfront_porch + hsync - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive + right_border + hfront_porch - 1));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive + bottom_border - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VSYNC(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((vactive + bottom_border + vfront_porch + vsync - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive + bottom_border + vfront_porch - 1));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_DISABLE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_WIN_POS(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPESRC(0), ((hactive - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_CTL(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_WIN_SZ(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PFIT_CONTROL, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPESRC(0), (639 << 16) | 399);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PFIT_CONTROL, 0x80000000);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_BPP_6);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VGACNTRL, VGA_DISP_DISABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | DISPPLANE_BGRX888);</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VGACNTRL, 0xc4008e);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + LVDS, LVDS_PORT_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | (hpolarity << 20) | (vpolarity << 21)</span><br><span style="color: hsl(0, 100%, 40%);">- | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_CLOCK_A_POWERUP_ALL</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_ENABLE_DITHER</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_PIPE(0));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable screen memory. */</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(1, vga_sr_read(1) & ~0x20);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear interrupts. */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DEIIR, 0xffffffff);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + SDEIIR, 0xffffffff);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- memset((void *) lfb, 0,</span><br><span style="color: hsl(0, 100%, 40%);">- edid->x_resolution * edid->y_resolution * 4);</span><br><span style="color: hsl(0, 100%, 40%);">- set_vbe_mode_info_valid(edid, lfb);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void gma_init_vga(const struct northbridge_intel_gm45_config *info,</span><br><span style="color: hsl(0, 100%, 40%);">- u8 *mmio, u32 physbase, u16 piobase, u32 lfb,</span><br><span style="color: hsl(0, 100%, 40%);">- struct edid *edid)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- struct edid_mode *mode;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 hactive, vactive, right_border, bottom_border;</span><br><span style="color: hsl(0, 100%, 40%);">- int hpolarity, vpolarity;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 target_frequency;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 smallest_err = 0xffffffff;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_p1 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_p2;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_n = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_m1 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_m2 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0x18, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set up GTT. */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 0x2000; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- outl((i << 2) | 1, piobase);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(physbase + (i << 12) + 1, piobase + 4);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VGA0, 0x31108);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VGA1, 0x31406);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + ADPA, ADPA_DAC_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_PIPE_A_SELECT</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_CRT_HOTPLUG_MONITOR_COLOR</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_CRT_HOTPLUG_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_USE_VGA_HVPOLARITY</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_VSYNC_CNTL_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_HSYNC_CNTL_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_DPMS_ON);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x7041c, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DPLL_MD(0), 0x3);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DPLL_MD(1), 0x3);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- vga_misc_write(0x67);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xff</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">- vga_cr_write(0x11, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i <= 0x18; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- vga_cr_write(i, cr[i]);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- udelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable screen memory to prevent garbage from appearing. */</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(1, vga_sr_read(1) | 0x20);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mode = &edid->mode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- hactive = edid->x_resolution;</span><br><span style="color: hsl(0, 100%, 40%);">- vactive = edid->y_resolution;</span><br><span style="color: hsl(0, 100%, 40%);">- right_border = mode->hborder;</span><br><span style="color: hsl(0, 100%, 40%);">- bottom_border = mode->vborder;</span><br><span style="color: hsl(0, 100%, 40%);">- hpolarity = (mode->phsync == '-');</span><br><span style="color: hsl(0, 100%, 40%);">- vpolarity = (mode->pvsync == '-');</span><br><span style="color: hsl(0, 100%, 40%);">- vsync = mode->vspw;</span><br><span style="color: hsl(0, 100%, 40%);">- hsync = mode->hspw;</span><br><span style="color: hsl(0, 100%, 40%);">- vblank = mode->vbl;</span><br><span style="color: hsl(0, 100%, 40%);">- hblank = mode->hbl;</span><br><span style="color: hsl(0, 100%, 40%);">- hfront_porch = mode->hso;</span><br><span style="color: hsl(0, 100%, 40%);">- vfront_porch = mode->vso;</span><br><span style="color: hsl(0, 100%, 40%);">- target_frequency = mode->pixel_clock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(1, 1);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(0x2, 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(0x3, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(0x4, 0xe);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(1, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(2, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(3, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(4, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(5, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(6, 0x5);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(7, 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0x10, 0x1);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0x11, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- edid->bytes_per_line = (edid->bytes_per_line + 63) & ~63;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | DISPPLANE_BGRX888);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPADDR(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPSTRIDE(0), edid->bytes_per_line);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPSURF(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 0x100; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- vga_textmode_init();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_p2 = target_frequency <= 225000 ? 10 : 5;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- u32 candn, candm1, candm2, candp1;</span><br><span style="color: hsl(0, 100%, 40%);">- for (candn = 1; candn <= 4; candn++) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (candm1 = 23; candm1 >= 17; candm1--) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (candm2 = 11; candm2 >= 5; candm2--) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (candp1 = 8; candp1 >= 1; candp1--) {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 m = 5 * (candm1 + 2) + (candm2 + 2);</span><br><span style="color: hsl(0, 100%, 40%);">- u32 p = candp1 * pixel_p2;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2);</span><br><span style="color: hsl(0, 100%, 40%);">- u32 dot = DIV_ROUND_CLOSEST(vco, p);</span><br><span style="color: hsl(0, 100%, 40%);">- u32 this_err = MAX(dot, target_frequency) -</span><br><span style="color: hsl(0, 100%, 40%);">- MIN(dot, target_frequency);</span><br><span style="color: hsl(0, 100%, 40%);">- if (this_err < smallest_err) {</span><br><span style="color: hsl(0, 100%, 40%);">- smallest_err= this_err;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_n = candn;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_m1 = candm1;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_m2 = candm2;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_p1 = candp1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (smallest_err == 0xffffffff) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Error: Couldn't find GFX clock divisors\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "Bringing up panel at resolution %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hactive, vactive);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "Borders %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- right_border, bottom_border);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "Blank %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hblank, vblank);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "Sync %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hsync, vsync);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "Front porch %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hfront_porch, vfront_porch);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, (info->gfx.use_spread_spectrum_clock</span><br><span style="color: hsl(0, 100%, 40%);">- ? "Spread spectrum clock\n" : "DREF clock\n"));</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "Polarities %d, %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hpolarity, vpolarity);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "Pixel clock %d kHz\n",</span><br><span style="color: hsl(0, 100%, 40%);">- BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /</span><br><span style="color: hsl(0, 100%, 40%);">- (pixel_n + 2) / (pixel_p1 * pixel_p2));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + FP0(0), (pixel_n << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (pixel_m1 << 8) | pixel_m2);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DPLL(0), DPLL_VCO_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL</span><br><span style="color: hsl(0, 100%, 40%);">- | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 :</span><br><span style="color: hsl(0, 100%, 40%);">- DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)</span><br><span style="color: hsl(0, 100%, 40%);">- | (0x10000 << (pixel_p1 - 1))</span><br><span style="color: hsl(0, 100%, 40%);">- | (6 << 9));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DPLL(0), DPLL_VCO_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL</span><br><span style="color: hsl(0, 100%, 40%);">- | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 :</span><br><span style="color: hsl(0, 100%, 40%);">- DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)</span><br><span style="color: hsl(0, 100%, 40%);">- | (0x10000 << (pixel_p1 - 1))</span><br><span style="color: hsl(0, 100%, 40%);">- | (6 << 9));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + ADPA, ADPA_DAC_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_PIPE_A_SELECT</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_CRT_HOTPLUG_MONITOR_COLOR</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_CRT_HOTPLUG_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_VSYNC_CNTL_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_HSYNC_CNTL_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_DPMS_ON</span><br><span style="color: hsl(0, 100%, 40%);">- | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW :</span><br><span style="color: hsl(0, 100%, 40%);">- ADPA_VSYNC_ACTIVE_HIGH)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW :</span><br><span style="color: hsl(0, 100%, 40%);">- ADPA_HSYNC_ACTIVE_HIGH));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + HTOTAL(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + HBLANK(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive + right_border - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + HSYNC(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hfront_porch + hsync - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive + right_border + hfront_porch - 1));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive + bottom_border - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VSYNC(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((vactive + bottom_border + vfront_porch + vsync - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive + bottom_border + vfront_porch - 1));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_DISABLE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_WIN_POS(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPESRC(0), ((hactive - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_CTL(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_WIN_SZ(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PFIT_CONTROL, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPESRC(0), (639 << 16) | 399);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PFIT_CONTROL, 0x80000000);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_BPP_6);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VGACNTRL, VGA_DISP_DISABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | DISPPLANE_BGRX888);</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VGACNTRL, 0xc4008e);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + ADPA, ADPA_DAC_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_PIPE_A_SELECT</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_CRT_HOTPLUG_MONITOR_COLOR</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_CRT_HOTPLUG_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_VSYNC_CNTL_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_HSYNC_CNTL_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_DPMS_ON</span><br><span style="color: hsl(0, 100%, 40%);">- | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW :</span><br><span style="color: hsl(0, 100%, 40%);">- ADPA_VSYNC_ACTIVE_HIGH)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW :</span><br><span style="color: hsl(0, 100%, 40%);">- ADPA_HSYNC_ACTIVE_HIGH));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable screen memory. */</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(1, vga_sr_read(1) & ~0x20);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear interrupts. */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DEIIR, 0xffffffff);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + SDEIIR, 0xffffffff);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- memset((void *) lfb, 0,</span><br><span style="color: hsl(0, 100%, 40%);">- edid->x_resolution * edid->y_resolution * 4);</span><br><span style="color: hsl(0, 100%, 40%);">- set_vbe_mode_info_valid(edid, lfb);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void gma_ngi(struct device *const dev, struct edid *edid_lvds)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u8 edid_data_vga[128];</span><br><span style="color: hsl(0, 100%, 40%);">- struct edid edid_vga;</span><br><span style="color: hsl(0, 100%, 40%);">- int vga_edid_status;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 *mmio;</span><br><span style="color: hsl(0, 100%, 40%);">- struct northbridge_intel_gm45_config *conf = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mmio = res2mmio(gtt_res, 0, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "VGA EDID\n");</span><br><span style="color: hsl(0, 100%, 40%);">- intel_gmbus_read_edid(mmio + GMBUS0, GMBUS_PORT_VGADDC, 0x50,</span><br><span style="color: hsl(0, 100%, 40%);">- edid_data_vga, sizeof(edid_data_vga));</span><br><span style="color: hsl(0, 100%, 40%);">- intel_gmbus_stop(mmio + GMBUS0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_edid_status = decode_edid(edid_data_vga,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(edid_data_vga), &edid_vga);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- u32 physbase;</span><br><span style="color: hsl(0, 100%, 40%);">- struct resource *lfb_res;</span><br><span style="color: hsl(0, 100%, 40%);">- struct resource *pio_res;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);</span><br><span style="color: hsl(0, 100%, 40%);">- pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- physbase = pci_read_config32(dev, 0x5c) & ~0xf;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!(physbase && pio_res && pio_res->base && lfb_res && lfb_res->base))</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "Initializing display without OPROM. MMIO 0x%llx\n",</span><br><span style="color: hsl(0, 100%, 40%);">- gtt_res->base);</span><br><span style="color: hsl(0, 100%, 40%);">- if (vga_edid_status != EDID_ABSENT) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Initialising display on VGA output\n");</span><br><span style="color: hsl(0, 100%, 40%);">- gma_init_vga(conf, mmio, physbase, pio_res->base, lfb_res->base,</span><br><span style="color: hsl(0, 100%, 40%);">- &edid_vga);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Initialising display on LVDS output\n");</span><br><span style="color: hsl(0, 100%, 40%);">- gma_init_lvds(conf, mmio, physbase, pio_res->base,</span><br><span style="color: hsl(0, 100%, 40%);">- lfb_res->base, edid_lvds);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Linux relies on VBT for panel info. */</span><br><span style="color: hsl(0, 100%, 40%);">- generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static u32 get_cdclk(struct device *const dev)</span><br><span> {</span><br><span> const u16 cdclk_sel =</span><br><span>@@ -745,6 +172,7 @@</span><br><span> u8 *mmio;</span><br><span> u8 edid_data_lvds[128];</span><br><span> struct edid edid_lvds;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct northbridge_intel_gm45_config *const conf = dev->chip_info;</span><br><span> </span><br><span> /* IGD needs to be Bus Master */</span><br><span> reg32 = pci_read_config32(dev, PCI_COMMAND);</span><br><span>@@ -771,11 +199,11 @@</span><br><span> /* Post VBIOS init */</span><br><span> gma_pm_init_post_vbios(dev, edid_lvds.ascii_string);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {</span><br><span style="color: hsl(0, 100%, 40%);">- gma_ngi(dev, &edid_lvds);</span><br><span style="color: hsl(0, 100%, 40%);">- } else if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {</span><br><span> int lightup_ok;</span><br><span> gma_gfxinit(&lightup_ok);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Linux relies on VBT for panel info. */</span><br><span style="color: hsl(120, 100%, 40%);">+ generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA");</span><br><span> }</span><br><span> </span><br><span> intel_gma_restore_opregion();</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27016">change 27016</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I540cf08cef6ff7825694ebfa36e2e6437916e657 </div>
<div style="display:none"> Gerrit-Change-Number: 27016 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>