<p>Cole Nelson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27019">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/{glk,apl}: ensure C1E is disabled after S3 resume<br><br>C1E is disabled by the kernel driver intel_idle at boot. This does not<br>address the S3 resume case, so we lose state and C1E is enabled after S3<br>resume.<br><br>Disable C1E for GLK as it is for APL. This gives a coherent state before<br>and after S3 resume.<br><br>TEST='iotools rdmsr cpu 0x1fc' after boot and S3 resume.<br><br>Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10<br>Signed-off-by: Cole Nelson <colex.nelson@intel.com><br>---<br>M src/soc/intel/apollolake/cpu.c<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>2 files changed, 3 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/27019/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c</span><br><span>index 4a7e40a..9337eb3 100644</span><br><span>--- a/src/soc/intel/apollolake/cpu.c</span><br><span>+++ b/src/soc/intel/apollolake/cpu.c</span><br><span>@@ -53,11 +53,11 @@</span><br><span> /* Power Management I/O base address for I/O trapping to C-states */</span><br><span> REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE,</span><br><span> (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))),</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable C1E */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),</span><br><span> /* Disable support for MONITOR and MWAIT instructions */</span><br><span> REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0),</span><br><span> #endif</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable C1E */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0),</span><br><span> /*</span><br><span> * Enable and Lock the Advanced Encryption Standard (AES-NI)</span><br><span> * feature register</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>index 22e8862..e1fc431 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>@@ -72,6 +72,7 @@</span><br><span> #define PRMRR_PHYS_MASK_LOCK (1 << 10)</span><br><span> #define PRMRR_PHYS_MASK_VALID (1 << 11)</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span style="color: hsl(120, 100%, 40%);">+#define POWER_CTL_C1E_MASK (1 << 1)</span><br><span> #define MSR_EVICT_CTL 0x2e0</span><br><span> #define MSR_SGX_OWNEREPOCH0 0x300</span><br><span> #define MSR_SGX_OWNEREPOCH1 0x301</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27019">change 27019</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27019"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10 </div>
<div style="display:none"> Gerrit-Change-Number: 27019 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Cole Nelson <colex.nelson@intel.com> </div>