<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27015">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Move constant to the right side of comparison<br><br>Change-Id: I76d35a3643600f81a6da7e0af99c935ebd1c2fc7<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/device/pci_rom.c<br>M src/northbridge/amd/agesa/family16kb/state_machine.c<br>M src/northbridge/amd/amdmct/mct/mctardk4.c<br>M src/southbridge/amd/cimx/sb800/late.c<br>4 files changed, 4 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/27015/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c</span><br><span>index 35d3d69..7bc18a1 100644</span><br><span>--- a/src/device/pci_rom.c</span><br><span>+++ b/src/device/pci_rom.c</span><br><span>@@ -151,7 +151,7 @@</span><br><span>          * whether the ROM image is for a VGA device because some</span><br><span>     * devices have a mismatch between the hardware and the ROM.</span><br><span>          */</span><br><span style="color: hsl(0, 100%, 40%);">-     if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) {</span><br><span style="color: hsl(120, 100%, 40%);">+    if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {</span><br><span> #if !IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)</span><br><span>          extern struct device *vga_pri; /* Primary VGA device (device.c). */</span><br><span>          if (dev != vga_pri) return NULL; /* Only one VGA supported. */</span><br><span>diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c</span><br><span>index 00a7e85..39f7a29 100644</span><br><span>--- a/src/northbridge/amd/agesa/family16kb/state_machine.c</span><br><span>+++ b/src/northbridge/amd/agesa/family16kb/state_machine.c</span><br><span>@@ -34,7 +34,7 @@</span><br><span> </span><br><span>  if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {</span><br><span>           status = OemInitResume(&Post->MemConfig.MemContext);</span><br><span style="color: hsl(0, 100%, 40%);">-             if (AGESA_SUCCESS == status)</span><br><span style="color: hsl(120, 100%, 40%);">+          if (status == AGESA_SUCCESS)</span><br><span>                         Post->MemConfig.MemRestoreCtl = 1;</span><br><span>        }</span><br><span> }</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c</span><br><span>index f7a4bee..d112c46 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct/mctardk4.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct/mctardk4.c</span><br><span>@@ -146,6 +146,6 @@</span><br><span>                        }</span><br><span>            }</span><br><span>            p+=10;</span><br><span style="color: hsl(0, 100%, 40%);">-  } while (0xFF == *p);</span><br><span style="color: hsl(120, 100%, 40%);">+ } while (*p == 0xff);</span><br><span>        }</span><br><span> }</span><br><span>diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c</span><br><span>index 30cddb2..45011b8 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb800/late.c</span><br><span>+++ b/src/southbridge/amd/cimx/sb800/late.c</span><br><span>@@ -387,7 +387,7 @@</span><br><span> </span><br><span>    case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */</span><br><span>            if (dev->enabled) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  if (AZALIA_DISABLE == sb_config->AzaliaController) {</span><br><span style="color: hsl(120, 100%, 40%);">+                       if (sb_config->AzaliaController == AZALIA_DISABLE) {</span><br><span>                              sb_config->AzaliaController = AZALIA_AUTO;</span><br><span>                        }</span><br><span>            } else {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27015">change 27015</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27015"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I76d35a3643600f81a6da7e0af99c935ebd1c2fc7 </div>
<div style="display:none"> Gerrit-Change-Number: 27015 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>