<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26974">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/lynxpoint: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I064ff5e76dd95c1770cd24139195b2a5fff2d382<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/lynxpoint/lpc.c<br>M src/southbridge/intel/lynxpoint/pci.c<br>M src/southbridge/intel/lynxpoint/pcie.c<br>M src/southbridge/intel/lynxpoint/sata.c<br>M src/southbridge/intel/lynxpoint/watchdog.c<br>5 files changed, 31 insertions(+), 31 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/26974/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>index d1d00c6..a2a6198 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>@@ -109,9 +109,9 @@</span><br><span>  * 0x80 - The PIRQ is not routed.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pirq_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pirq_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-     device_t irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+     struct device *irq_dev;</span><br><span>      /* Get the chip configuration */</span><br><span>     config_t *config = dev->chip_info;</span><br><span> </span><br><span>@@ -151,7 +151,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_gpi_routing(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_gpi_routing(struct device *dev)</span><br><span> {</span><br><span>    /* Get the chip configuration */</span><br><span>     config_t *config = dev->chip_info;</span><br><span>@@ -180,7 +180,7 @@</span><br><span>  pci_write_config32(dev, GPIO_ROUT, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_power_options(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_power_options(struct device *dev)</span><br><span> {</span><br><span>       u8 reg8;</span><br><span>     u16 reg16;</span><br><span>@@ -420,7 +420,7 @@</span><br><span>     reg32 = RCBA32(HPTC);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_clock_gating(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_clock_gating(struct device *dev)</span><br><span> {</span><br><span>        /* LynxPoint Mobile */</span><br><span>       u32 reg32;</span><br><span>@@ -445,7 +445,7 @@</span><br><span>     RCBA32_OR(0x38c0, 0x7); // SPI Dynamic</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_lp_clock_gating(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_lp_clock_gating(struct device *dev)</span><br><span> {</span><br><span>         /* LynxPoint LP */</span><br><span>   u32 reg32;</span><br><span>@@ -595,7 +595,7 @@</span><br><span>     pch_fixups(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_add_mmio_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_add_mmio_resources(struct device *dev)</span><br><span> {</span><br><span>       u32 reg;</span><br><span>     struct resource *res;</span><br><span>@@ -657,7 +657,7 @@</span><br><span>  * Note: this function assumes there is no overlap with the default LPC device's</span><br><span>  * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index)</span><br><span> {</span><br><span>    struct resource *res;</span><br><span> </span><br><span>@@ -670,7 +670,7 @@</span><br><span>      res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index)</span><br><span> {</span><br><span>        /*</span><br><span>    * Check if the register is enabled. If so and the base exceeds the</span><br><span>@@ -683,7 +683,7 @@</span><br><span>    }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_add_io_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_add_io_resources(struct device *dev)</span><br><span> {</span><br><span>  struct resource *res;</span><br><span>        config_t *config = dev->chip_info;</span><br><span>@@ -708,7 +708,7 @@</span><br><span>  pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span>  global_nvs_t *gnvs;</span><br><span> </span><br><span>@@ -727,7 +727,7 @@</span><br><span>                memset(gnvs, 0, sizeof(global_nvs_t));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_enable(struct device *dev)</span><br><span> {</span><br><span>         /* Enable PCH Display Port */</span><br><span>        RCBA16(DISPBDF) = 0x0010;</span><br><span>@@ -736,7 +736,7 @@</span><br><span>      pch_enable(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>     if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -747,7 +747,7 @@</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_inject_dsdt(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_inject_dsdt(struct device *dev)</span><br><span> {</span><br><span>    global_nvs_t *gnvs;</span><br><span> </span><br><span>@@ -788,7 +788,7 @@</span><br><span>        }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static unsigned long southbridge_write_acpi_tables(device_t device,</span><br><span style="color: hsl(120, 100%, 40%);">+static unsigned long southbridge_write_acpi_tables(struct device *device,</span><br><span>                                                unsigned long start,</span><br><span>                                                 struct acpi_rsdp *rsdp)</span><br><span> {</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pci.c b/src/southbridge/intel/lynxpoint/pci.c</span><br><span>index e2e052b..3c43210 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pci.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pci.c</span><br><span>@@ -104,7 +104,7 @@</span><br><span>       ich_pci_dev_enable_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>   /* NOTE: This is not the default position! */</span><br><span>        if (!vendor || !device) {</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c</span><br><span>index 73c81b4..590a7e2 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pcie.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pcie.c</span><br><span>@@ -42,7 +42,7 @@</span><br><span>   int coalesce;</span><br><span>        int gbe_port;</span><br><span>        int num_ports;</span><br><span style="color: hsl(0, 100%, 40%);">-  device_t ports[MAX_NUM_ROOT_PORTS];</span><br><span style="color: hsl(120, 100%, 40%);">+   struct device *ports[MAX_NUM_ROOT_PORTS];</span><br><span> };</span><br><span> </span><br><span> static struct root_port_config rpc;</span><br><span>@@ -55,18 +55,18 @@</span><br><span>             return H_NUM_ROOT_PORTS;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline int root_port_is_first(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int root_port_is_first(struct device *dev)</span><br><span> {</span><br><span>   return PCI_FUNC(dev->path.pci.devfn) == 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline int root_port_is_last(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int root_port_is_last(struct device *dev)</span><br><span> {</span><br><span>        return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1);</span><br><span> }</span><br><span> </span><br><span> /* Root ports are numbered 1..N in the documentation. */</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int root_port_number(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int root_port_number(struct device *dev)</span><br><span> {</span><br><span>    return PCI_FUNC(dev->path.pci.devfn) + 1;</span><br><span> }</span><br><span>@@ -101,7 +101,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void root_port_init_config(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void root_port_init_config(struct device *dev)</span><br><span> {</span><br><span>        int rp;</span><br><span> </span><br><span>@@ -154,7 +154,7 @@</span><br><span> /* Update devicetree with new Root Port function number assignment */</span><br><span> static void pch_pcie_device_set_func(int index, int pci_func)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-        device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  unsigned new_devfn;</span><br><span> </span><br><span>      dev = rpc.ports[index];</span><br><span>@@ -187,7 +187,7 @@</span><br><span>        enabled_ports = 0;</span><br><span> </span><br><span>       for (i = 0; i < rpc.num_ports; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+         struct device *dev;</span><br><span>          int rp;</span><br><span> </span><br><span>          dev = rpc.ports[i];</span><br><span>@@ -275,7 +275,7 @@</span><br><span>    pcie_enable_clock_gating();</span><br><span> </span><br><span>      for (i = 0; i < rpc.num_ports; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+         struct device *dev;</span><br><span>          u32 reg32;</span><br><span> </span><br><span>               dev = rpc.ports[i];</span><br><span>@@ -328,7 +328,7 @@</span><br><span>    RCBA32(RPFN) = rpc.new_rpfn;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void root_port_mark_disable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void root_port_mark_disable(struct device *dev)</span><br><span> {</span><br><span>   /* Mark device as disabled. */</span><br><span>       dev->enabled = 0;</span><br><span>@@ -336,7 +336,7 @@</span><br><span>   rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void root_port_check_disable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void root_port_check_disable(struct device *dev)</span><br><span> {</span><br><span>         int rp;</span><br><span>      int is_lp;</span><br><span>@@ -695,7 +695,7 @@</span><br><span>     pci_write_config16(dev, 0x1e, reg16);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pcie_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pcie_enable(struct device *dev)</span><br><span> {</span><br><span>        /* Add this device to the root port config structure. */</span><br><span>     root_port_init_config(dev);</span><br><span>@@ -715,7 +715,7 @@</span><br><span>            root_port_commit_config();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>         /* NOTE: This is not the default position! */</span><br><span>        if (!vendor || !device) {</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c</span><br><span>index c45579b..7dd7ce6 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/sata.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/sata.c</span><br><span>@@ -301,7 +301,7 @@</span><br><span>         pci_write_config32(dev, 0x300, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_enable(struct *dev)</span><br><span> {</span><br><span>      /* Get the chip configuration */</span><br><span>     config_t *config = dev->chip_info;</span><br><span>@@ -322,7 +322,7 @@</span><br><span>  pci_write_config16(dev, 0x90, map);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>        if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/watchdog.c b/src/southbridge/intel/lynxpoint/watchdog.c</span><br><span>index 74f69b0..9f30f03 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/watchdog.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/watchdog.c</span><br><span>@@ -28,7 +28,7 @@</span><br><span>   //</span><br><span> void watchdog_off(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-       device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct *dev;</span><br><span>         unsigned long value, base;</span><br><span> </span><br><span>       /* Turn off the ICH7 watchdog. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26974">change 26974</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26974"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I064ff5e76dd95c1770cd24139195b2a5fff2d382 </div>
<div style="display:none"> Gerrit-Change-Number: 26974 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>