<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26967">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/x4x: Depreciate native graphic init<br><br>Libgfxinit provides a better alternative to the native C init. While<br>libgfxinit mandates an ada compiler, we want to encourage use of it<br>since it is in much better shape and is actually maintained.<br><br>This way libgfxinit also gets build-tested by Jenkins.<br><br>Change-Id: I4843f52307b87cff6fa6f4d0c74b87428fefa8ac<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/asrock/g41c-gs/Kconfig<br>M src/mainboard/foxconn/g41s-k/Kconfig<br>M src/mainboard/gigabyte/ga-g41m-es2l/Kconfig<br>M src/mainboard/intel/dg41wv/Kconfig<br>M src/mainboard/intel/dg43gt/Kconfig<br>M src/northbridge/intel/x4x/Kconfig<br>M src/northbridge/intel/x4x/gma.c<br>7 files changed, 1 insertion(+), 349 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/26967/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig</span><br><span>index b657a36..31e6a6b 100644</span><br><span>--- a/src/mainboard/asrock/g41c-gs/Kconfig</span><br><span>+++ b/src/mainboard/asrock/g41c-gs/Kconfig</span><br><span>@@ -25,8 +25,6 @@</span><br><span> select SUPERIO_NUVOTON_NCT6776</span><br><span> select HAVE_ACPI_TABLES</span><br><span> select BOARD_ROMSIZE_KB_1024</span><br><span style="color: hsl(0, 100%, 40%);">- select INTEL_EDID</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_NATIVE_VGA_INIT</span><br><span> select PCIEXP_ASPM</span><br><span> select PCIEXP_CLK_PM</span><br><span> select PCIEXP_L1_SUB_STATE</span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/Kconfig b/src/mainboard/foxconn/g41s-k/Kconfig</span><br><span>index e30bdf1..95a73cb 100644</span><br><span>--- a/src/mainboard/foxconn/g41s-k/Kconfig</span><br><span>+++ b/src/mainboard/foxconn/g41s-k/Kconfig</span><br><span>@@ -28,9 +28,7 @@</span><br><span> select HAVE_ACPI_TABLES</span><br><span> select HAVE_CMOS_DEFAULT</span><br><span> select HAVE_OPTION_TABLE</span><br><span style="color: hsl(0, 100%, 40%);">- select INTEL_EDID</span><br><span> select MAINBOARD_HAS_LPC_TPM</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_NATIVE_VGA_INIT</span><br><span> select PCIEXP_ASPM</span><br><span> select PCIEXP_CLK_PM</span><br><span> select PCIEXP_L1_SUB_STATE</span><br><span>diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig</span><br><span>index 811f5c4..bc777c5 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig</span><br><span>+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig</span><br><span>@@ -24,8 +24,6 @@</span><br><span> select SUPERIO_ITE_IT8718F</span><br><span> select HAVE_ACPI_TABLES</span><br><span> select BOARD_ROMSIZE_KB_1024</span><br><span style="color: hsl(0, 100%, 40%);">- select INTEL_EDID</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_NATIVE_VGA_INIT</span><br><span> select PCIEXP_ASPM</span><br><span> select PCIEXP_CLK_PM</span><br><span> select PCIEXP_L1_SUB_STATE</span><br><span>diff --git a/src/mainboard/intel/dg41wv/Kconfig b/src/mainboard/intel/dg41wv/Kconfig</span><br><span>index dfccf64..ecbedda 100644</span><br><span>--- a/src/mainboard/intel/dg41wv/Kconfig</span><br><span>+++ b/src/mainboard/intel/dg41wv/Kconfig</span><br><span>@@ -25,8 +25,6 @@</span><br><span> select SUPERIO_WINBOND_W83627DHG</span><br><span> select HAVE_ACPI_TABLES</span><br><span> select BOARD_ROMSIZE_KB_2048</span><br><span style="color: hsl(0, 100%, 40%);">- select INTEL_EDID</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_NATIVE_VGA_INIT</span><br><span> select PCIEXP_ASPM</span><br><span> select PCIEXP_CLK_PM</span><br><span> select PCIEXP_L1_SUB_STATE</span><br><span>diff --git a/src/mainboard/intel/dg43gt/Kconfig b/src/mainboard/intel/dg43gt/Kconfig</span><br><span>index 2a05098..d6ba96d 100644</span><br><span>--- a/src/mainboard/intel/dg43gt/Kconfig</span><br><span>+++ b/src/mainboard/intel/dg43gt/Kconfig</span><br><span>@@ -30,8 +30,6 @@</span><br><span> select HAVE_OPTION_TABLE</span><br><span> select HAVE_CMOS_DEFAULT</span><br><span> select HAVE_ACPI_RESUME</span><br><span style="color: hsl(0, 100%, 40%);">- select INTEL_EDID</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_NATIVE_VGA_INIT</span><br><span> select GFX_GMA_ANALOG_I2C_HDMI_C</span><br><span> select DRIVERS_I2C_CK505</span><br><span> select INTEL_GMA_VBT_HAVE_DATA_FILE</span><br><span>diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig</span><br><span>index 6e3a19c..1c65614 100644</span><br><span>--- a/src/northbridge/intel/x4x/Kconfig</span><br><span>+++ b/src/northbridge/intel/x4x/Kconfig</span><br><span>@@ -25,8 +25,6 @@</span><br><span> select LAPIC_MONOTONIC_TIMER</span><br><span> select VGA</span><br><span> select INTEL_GMA_ACPI</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span> select CACHE_MRC_SETTINGS</span><br><span> select POSTCAR_STAGE</span><br><span> select POSTCAR_CONSOLE</span><br><span>diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c</span><br><span>index f38d64d..2d2feee 100644</span><br><span>--- a/src/northbridge/intel/x4x/gma.c</span><br><span>+++ b/src/northbridge/intel/x4x/gma.c</span><br><span>@@ -58,335 +58,6 @@</span><br><span> gnvs_ptr->aslb = aslb;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u8 edid_is_present(u8 *edid, u32 edid_size)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 i;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < edid_size; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (*(edid + i) != 0)</span><br><span style="color: hsl(0, 100%, 40%);">- return 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_gma_init(const struct northbridge_intel_x4x_config *info,</span><br><span style="color: hsl(0, 100%, 40%);">- u8 *mmio, u32 physbase, u16 piobase, u32 lfb)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 edid_data[128];</span><br><span style="color: hsl(0, 100%, 40%);">- struct edid edid;</span><br><span style="color: hsl(0, 100%, 40%);">- struct edid_mode *mode;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 edid_is_found;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Initialise mode variables for 640 x 480 @ 60Hz */</span><br><span style="color: hsl(0, 100%, 40%);">- u32 hactive = 640, vactive = 480;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 right_border = 0, bottom_border = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- int hpolarity = 0, vpolarity = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 hsync = 96, vsync = 2;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 hblank = 160, vblank = 45;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 hfront_porch = 16, vfront_porch = 10;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 target_frequency = 25175;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- u32 err_most = 0xffffffff;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_p1 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_p2;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_n = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_m1 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_m2 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- u8 vga_gmbus = GMBUS_PORT_VGADDC;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_GFX_GMA_ANALOG_I2C_HDMI_B))</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gmbus = GMBUS_PORT_DPB;</span><br><span style="color: hsl(0, 100%, 40%);">- else if (IS_ENABLED(CONFIG_GFX_GMA_ANALOG_I2C_HDMI_C))</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gmbus = GMBUS_PORT_DPC;</span><br><span style="color: hsl(0, 100%, 40%);">- else if (IS_ENABLED(CONFIG_GFX_GMA_ANALOG_I2C_HDMI_D))</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gmbus = GMBUS_PORT_DPD;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0x18, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set up GTT */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 0x1000; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- outl((i << 2) | 1, piobase);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(physbase + (i << 12) + 1, piobase + 4);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VGA0, 0x31108);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VGA1, 0x31406);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + ADPA, ADPA_DAC_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_PIPE_A_SELECT</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_CRT_HOTPLUG_MONITOR_COLOR</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_CRT_HOTPLUG_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_USE_VGA_HVPOLARITY</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_VSYNC_CNTL_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_HSYNC_CNTL_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_DPMS_ON</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x7041c, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DPLL_MD(0), 0x3);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DPLL_MD(1), 0x3);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- vga_misc_write(0x67);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xff</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">- vga_cr_write(0x11, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i <= 0x18; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- vga_cr_write(i, cr[i]);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- udelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * TODO: check if it is actually an analog display.</span><br><span style="color: hsl(0, 100%, 40%);">- * No harm is done but the console output could be confusing.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- intel_gmbus_read_edid(mmio + GMBUS0, vga_gmbus, 0x50, edid_data,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(edid_data));</span><br><span style="color: hsl(0, 100%, 40%);">- intel_gmbus_stop(mmio + GMBUS0);</span><br><span style="color: hsl(0, 100%, 40%);">- decode_edid(edid_data,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(edid_data), &edid);</span><br><span style="color: hsl(0, 100%, 40%);">- mode = &edid.mode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable screen memory to prevent garbage from appearing. */</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(1, vga_sr_read(1) | 0x20);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- edid_is_found = edid_is_present(edid_data, sizeof(edid_data));</span><br><span style="color: hsl(0, 100%, 40%);">- if (edid_is_found) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "EDID is not null");</span><br><span style="color: hsl(0, 100%, 40%);">- hactive = edid.x_resolution;</span><br><span style="color: hsl(0, 100%, 40%);">- vactive = edid.y_resolution;</span><br><span style="color: hsl(0, 100%, 40%);">- right_border = mode->hborder;</span><br><span style="color: hsl(0, 100%, 40%);">- bottom_border = mode->vborder;</span><br><span style="color: hsl(0, 100%, 40%);">- hpolarity = (mode->phsync == '-');</span><br><span style="color: hsl(0, 100%, 40%);">- vpolarity = (mode->pvsync == '-');</span><br><span style="color: hsl(0, 100%, 40%);">- vsync = mode->vspw;</span><br><span style="color: hsl(0, 100%, 40%);">- hsync = mode->hspw;</span><br><span style="color: hsl(0, 100%, 40%);">- vblank = mode->vbl;</span><br><span style="color: hsl(0, 100%, 40%);">- hblank = mode->hbl;</span><br><span style="color: hsl(0, 100%, 40%);">- hfront_porch = mode->hso;</span><br><span style="color: hsl(0, 100%, 40%);">- vfront_porch = mode->vso;</span><br><span style="color: hsl(0, 100%, 40%);">- target_frequency = mode->pixel_clock;</span><br><span style="color: hsl(0, 100%, 40%);">- } else</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(1, 1);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(0x2, 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(0x3, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(0x4, 0xe);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(1, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(2, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(3, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(4, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(5, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(6, 0x5);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(7, 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0x10, 0x1);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0x11, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | DISPPLANE_BGRX888);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPADDR(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPSURF(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 0x100; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- vga_textmode_init();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_p2 = target_frequency <= 225000 ? 10 : 5;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- u32 candn, candm1, candm2, candp1;</span><br><span style="color: hsl(0, 100%, 40%);">- for (candn = 1; candn <= 4; candn++) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (candm1 = 23; candm1 >= 16; candm1--) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (candm2 = 11; candm2 >= 5; candm2--) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (candp1 = 8; candp1 >= 1; candp1--) {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 m = 5 * (candm1 + 2) + (candm2 + 2);</span><br><span style="color: hsl(0, 100%, 40%);">- u32 p = candp1 * pixel_p2;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 vco = DIV_ROUND_CLOSEST(</span><br><span style="color: hsl(0, 100%, 40%);">- BASE_FREQUENCY * m, candn + 2);</span><br><span style="color: hsl(0, 100%, 40%);">- u32 dot = DIV_ROUND_CLOSEST(vco, p);</span><br><span style="color: hsl(0, 100%, 40%);">- u32 this_err = MAX(dot, target_frequency) -</span><br><span style="color: hsl(0, 100%, 40%);">- MIN(dot, target_frequency);</span><br><span style="color: hsl(0, 100%, 40%);">- if (this_err < err_most) {</span><br><span style="color: hsl(0, 100%, 40%);">- err_most = this_err;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_n = candn;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_m1 = candm1;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_m2 = candm2;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_p1 = candp1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (err_most == 0xffffffff) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Couldn't find GFX clock divisors\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hactive, vactive);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Borders %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- right_border, bottom_border);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Blank %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hblank, vblank);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Sync %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hsync, vsync);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Front porch %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hfront_porch, vfront_porch);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock</span><br><span style="color: hsl(0, 100%, 40%);">- ? "Spread spectrum clock\n" : "DREF clock\n"));</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Polarities %d, %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hpolarity, vpolarity);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Pixel clock %d kHz\n",</span><br><span style="color: hsl(0, 100%, 40%);">- BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /</span><br><span style="color: hsl(0, 100%, 40%);">- (pixel_n + 2) / (pixel_p1 * pixel_p2));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + FP0(0), (pixel_n << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (pixel_m1 << 8) | pixel_m2);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DPLL(0), DPLL_VCO_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL</span><br><span style="color: hsl(0, 100%, 40%);">- | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 :</span><br><span style="color: hsl(0, 100%, 40%);">- DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)</span><br><span style="color: hsl(0, 100%, 40%);">- | (0x10000 << (pixel_p1 - 1))</span><br><span style="color: hsl(0, 100%, 40%);">- | (6 << 9));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DPLL(0), DPLL_VCO_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL</span><br><span style="color: hsl(0, 100%, 40%);">- | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 :</span><br><span style="color: hsl(0, 100%, 40%);">- DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)</span><br><span style="color: hsl(0, 100%, 40%);">- | (0x10000 << (pixel_p1 - 1))</span><br><span style="color: hsl(0, 100%, 40%);">- | (6 << 9));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + ADPA, ADPA_DAC_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_PIPE_A_SELECT</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_CRT_HOTPLUG_MONITOR_COLOR</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_CRT_HOTPLUG_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_VSYNC_CNTL_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_HSYNC_CNTL_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_DPMS_ON</span><br><span style="color: hsl(0, 100%, 40%);">- | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW :</span><br><span style="color: hsl(0, 100%, 40%);">- ADPA_VSYNC_ACTIVE_HIGH)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW :</span><br><span style="color: hsl(0, 100%, 40%);">- ADPA_HSYNC_ACTIVE_HIGH));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + HTOTAL(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + HBLANK(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive + right_border - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + HSYNC(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hfront_porch + hsync - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive + right_border + hfront_porch - 1));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive + bottom_border - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VSYNC(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((vactive + bottom_border + vfront_porch + vsync - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive + bottom_border + vfront_porch - 1));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_DISABLE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_WIN_POS(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPESRC(0), ((hactive - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_CTL(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_WIN_SZ(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PFIT_CONTROL, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPESRC(0), (639 << 16) | 399);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PFIT_CONTROL, 0x80000000);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_BPP_6);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VGACNTRL, VGA_DISP_DISABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | DISPPLANE_BGRX888);</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VGACNTRL, 0xc4008e);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + ADPA, ADPA_DAC_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_PIPE_A_SELECT</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_CRT_HOTPLUG_MONITOR_COLOR</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_CRT_HOTPLUG_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_VSYNC_CNTL_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_HSYNC_CNTL_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | ADPA_DPMS_ON</span><br><span style="color: hsl(0, 100%, 40%);">- | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW :</span><br><span style="color: hsl(0, 100%, 40%);">- ADPA_VSYNC_ACTIVE_HIGH)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW :</span><br><span style="color: hsl(0, 100%, 40%);">- ADPA_HSYNC_ACTIVE_HIGH));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable screen memory. */</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(1, vga_sr_read(1) & ~0x20);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear interrupts. */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DEIIR, 0xffffffff);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + SDEIIR, 0xffffffff);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- memset((void *) lfb, 0,</span><br><span style="color: hsl(0, 100%, 40%);">- hactive * vactive * 4);</span><br><span style="color: hsl(0, 100%, 40%);">- set_vbe_mode_info_valid(&edid, lfb);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void native_init(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct resource *lfb_res;</span><br><span style="color: hsl(0, 100%, 40%);">- struct resource *pio_res;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 physbase;</span><br><span style="color: hsl(0, 100%, 40%);">- struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);</span><br><span style="color: hsl(0, 100%, 40%);">- struct northbridge_intel_x4x_config *conf = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);</span><br><span style="color: hsl(0, 100%, 40%);">- pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);</span><br><span style="color: hsl(0, 100%, 40%);">- physbase = pci_read_config32(dev, 0x5c) & ~0xf;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (gtt_res && gtt_res->base) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW,</span><br><span style="color: hsl(0, 100%, 40%);">- "Initializing VGA without OPROM. MMIO 0x%llx\n",</span><br><span style="color: hsl(0, 100%, 40%);">- gtt_res->base);</span><br><span style="color: hsl(0, 100%, 40%);">- intel_gma_init(conf, res2mmio(gtt_res, 0, 0),</span><br><span style="color: hsl(0, 100%, 40%);">- physbase, pio_res->base, lfb_res->base);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Linux relies on VBT for panel info. */</span><br><span style="color: hsl(0, 100%, 40%);">- generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void gma_func0_init(struct device *dev)</span><br><span> {</span><br><span> u16 reg16, ggc;</span><br><span>@@ -405,14 +76,7 @@</span><br><span> </span><br><span> ggc = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (ggc & (1 << 1)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "VGA cycles not assigned to IGD. "</span><br><span style="color: hsl(0, 100%, 40%);">- "Not running native graphic init.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- native_init(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- } else if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {</span><br><span> int lightup_ok;</span><br><span> gma_gfxinit(&lightup_ok);</span><br><span> } else {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26967">change 26967</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26967"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4843f52307b87cff6fa6f4d0c74b87428fefa8ac </div>
<div style="display:none"> Gerrit-Change-Number: 26967 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>