<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26943">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/{skl,cnl,apl}: Move common UART code to common block<br><br>Move common UART related function to common block instead of keeping it<br>inside each soc folder.<br>This will reduce redundant function across all soc.<br><br>BUG=none<br>BRANCH=none<br>TEST=code compiles fine for all platfrom<br><br>Change-Id: Ia583262d07e1c1ed2105fed25fbd5c8adb07c994<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/soc/intel/apollolake/bootblock/bootblock.c<br>D src/soc/intel/apollolake/include/soc/uart.h<br>M src/soc/intel/apollolake/romstage.c<br>M src/soc/intel/apollolake/uart.c<br>M src/soc/intel/cannonlake/bootblock/bootblock.c<br>M src/soc/intel/cannonlake/include/soc/pch.h<br>M src/soc/intel/cannonlake/uart.c<br>M src/soc/intel/common/block/include/intelblocks/uart.h<br>M src/soc/intel/common/block/uart/uart.c<br>M src/soc/intel/skylake/bootblock/bootblock.c<br>M src/soc/intel/skylake/include/soc/bootblock.h<br>M src/soc/intel/skylake/uart.c<br>12 files changed, 92 insertions(+), 114 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/26943/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>index 392237f..85baf5b 100644</span><br><span>--- a/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>+++ b/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>@@ -24,13 +24,13 @@</span><br><span> #include <intelblocks/rtc.h></span><br><span> #include <intelblocks/systemagent.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/uart.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/cpu.h></span><br><span> #include <soc/gpio.h></span><br><span> #include <soc/systemagent.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/uart.h></span><br><span> #include <spi-generic.h></span><br><span> #include <timestamp.h></span><br><span> </span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h</span><br><span>deleted file mode 100644</span><br><span>index bf8b9d7..0000000</span><br><span>--- a/src/soc/intel/apollolake/include/soc/uart.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,24 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(0, 100%, 40%);">- * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef _SOC_APOLLOLAKE_UART_H_</span><br><span style="color: hsl(0, 100%, 40%);">-#define _SOC_APOLLOLAKE_UART_H_</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Initialize the console UART including the pads for the configured UART. */</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_uart_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* _SOC_APOLLOLAKE_UART_H_ */</span><br><span>diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c</span><br><span>index 1a25105..4168771 100644</span><br><span>--- a/src/soc/intel/apollolake/romstage.c</span><br><span>+++ b/src/soc/intel/apollolake/romstage.c</span><br><span>@@ -47,7 +47,6 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pm.h></span><br><span> #include <soc/romstage.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/uart.h></span><br><span> #include <spi_flash.h></span><br><span> #include <string.h></span><br><span> #include <timestamp.h></span><br><span>diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c</span><br><span>index f9a4c8b..27f79e1 100644</span><br><span>--- a/src/soc/intel/apollolake/uart.c</span><br><span>+++ b/src/soc/intel/apollolake/uart.c</span><br><span>@@ -21,12 +21,10 @@</span><br><span> */</span><br><span> </span><br><span> #include <console/uart.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <intelblocks/uart.h></span><br><span> #include <soc/gpio.h></span><br><span> #include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/uart.h></span><br><span> </span><br><span> static const struct pad_config uart_gpios[] = {</span><br><span> #if IS_ENABLED(CONFIG_SOC_INTEL_GLK)</span><br><span>@@ -46,20 +44,18 @@</span><br><span> #endif</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void pch_uart_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *soc_get_gpio_pad(uint8_t pad_index)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * For APL, we have UART1 and UART2 valid.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Making an index 0 based for an array</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t array_index = pad_index - 1;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Get a 0-based pad index. See invalid_uart_for_console() above. */</span><br><span style="color: hsl(0, 100%, 40%);">- const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((array_index * 2) < sizeof(uart_gpios))</span><br><span style="color: hsl(120, 100%, 40%);">+ return &uart_gpios[array_index * 2];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Configure the 2 pads per UART. */</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_configure_pads(&uart_gpios[pad_index * 2], 2);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Program UART2 BAR0, command, reset and clock register */</span><br><span style="color: hsl(0, 100%, 40%);">- uart_common_init(uart, base);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Invalid UART console index selected for soc");</span><br><span> }</span><br><span> </span><br><span> uintptr_t uart_platform_base(int idx)</span><br><span>diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c</span><br><span>index b7e7797..ad18696 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/bootblock.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <bootblock_common.h></span><br><span> #include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/uart.h></span><br><span> #include <soc/bootblock.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/pch.h></span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h</span><br><span>index 53dd66a..da64a7a8 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/pch.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/pch.h</span><br><span>@@ -29,6 +29,5 @@</span><br><span> #define PCIE_CLK_FREE 0x80</span><br><span> </span><br><span> void pch_log_state(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_uart_init(void);</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c</span><br><span>index 6babe61..70657ac 100644</span><br><span>--- a/src/soc/intel/cannonlake/uart.c</span><br><span>+++ b/src/soc/intel/cannonlake/uart.c</span><br><span>@@ -30,49 +30,23 @@</span><br><span> #define PCR_SERIAL_IO_GPPRVRW7 0x618</span><br><span> #define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const struct port {</span><br><span style="color: hsl(0, 100%, 40%);">- struct pad_config pads[2]; /* just TX and RX */</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(0, 100%, 40%);">-} uart_ports[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {.dev = PCH_DEV_UART0,</span><br><span style="color: hsl(0, 100%, 40%);">- .pads = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* RX */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1)} /* TX */</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- {.dev = PCH_DEV_UART1,</span><br><span style="color: hsl(0, 100%, 40%);">- .pads = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* RX */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1)} /* TX */</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- {.dev = PCH_DEV_UART2,</span><br><span style="color: hsl(0, 100%, 40%);">- .pads = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* RX */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1)} /* TX */</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config uart_gpios[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /*UART0 RX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /*UART0 TX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /*UART1 RX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /*UART1 TX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /*UART2 RX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1) /*UART2 TX */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void pch_uart_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *soc_get_gpio_pad(uint8_t pad_index)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t base;</span><br><span style="color: hsl(0, 100%, 40%);">- const struct port *p;</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((pad_index * 2) < sizeof(uart_gpios))</span><br><span style="color: hsl(120, 100%, 40%);">+ return &uart_gpios[pad_index * 2];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- assert(CONFIG_UART_FOR_CONSOLE < ARRAY_SIZE(uart_ports));</span><br><span style="color: hsl(0, 100%, 40%);">- p = &uart_ports[CONFIG_UART_FOR_CONSOLE];</span><br><span style="color: hsl(0, 100%, 40%);">- base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- uart_common_init(p->dev, base);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Put UART2 in byte access mode for 16550 compatibility */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,</span><br><span style="color: hsl(0, 100%, 40%);">- PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Dummy read after setting any of GPPRVRW7.</span><br><span style="color: hsl(0, 100%, 40%);">- * Required for UART 16550 8-bit Legacy mode to become active</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- lpss_clk_read(base);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Invalid UART console index for soc");</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h</span><br><span>index 2734810..653918f 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/uart.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/uart.h</span><br><span>@@ -44,6 +44,10 @@</span><br><span> */</span><br><span> bool uart_is_debug_controller(struct device *dev);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * BootBlock pre initialization of UART console</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_uart_init(void);</span><br><span> /**************************** SoC callbacks ***********************************/</span><br><span> </span><br><span> void pch_uart_read_resources(struct device *dev);</span><br><span>@@ -61,6 +65,18 @@</span><br><span> device_t soc_uart_console_to_device(uint8_t uart_console);</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Get GPIO configuration pad for UART console</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Input:</span><br><span style="color: hsl(120, 100%, 40%);">+ * UART console index selected in config</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Returns:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Pointer to pad_config structure if valid UART index</span><br><span style="color: hsl(120, 100%, 40%);">+ * NULL = otherwise</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *soc_get_gpio_pad(uint8_t pad_index);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span> * Get UART debug controller device structure</span><br><span> *</span><br><span> * Returns:</span><br><span>diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c</span><br><span>index 1717cd6..dd14e3a 100644</span><br><span>--- a/src/soc/intel/common/block/uart/uart.c</span><br><span>+++ b/src/soc/intel/common/block/uart/uart.c</span><br><span>@@ -17,19 +17,27 @@</span><br><span> #include <assert.h></span><br><span> #include <compiler.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/uart.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <device/pci_ids.h></span><br><span> #include <device/pci_ops.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gpio.h></span><br><span> #include <intelblocks/lpss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span> #include <intelblocks/uart.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span> </span><br><span> #define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Serial IO UART controller legacy mode */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_SERIAL_IO_GPPRVRW7 0x618</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void uart_lpss_init(uintptr_t baseaddr)</span><br><span> {</span><br><span> /* Take UART out of reset */</span><br><span>@@ -90,6 +98,35 @@</span><br><span> return !lpss_is_controller_in_reset(base);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void pch_uart_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t uart = pch_uart_get_device();</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct pad_config *uart_gpios = soc_get_gpio_pad(</span><br><span style="color: hsl(120, 100%, 40%);">+ CONFIG_UART_FOR_CONSOLE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program UART2 BAR0, command, reset and clock register */</span><br><span style="color: hsl(120, 100%, 40%);">+ uart_common_init(uart, base);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if (!IS_ENABLED(CONFIG_SOC_INTEL_APOLLOLAKE))</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Put UART2 in byte access mode for 16550 compatibility */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Dummy read after setting any of GPPRVRW7.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Required for UART 16550 8-bit Legacy mode to become active</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ lpss_clk_read(base);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure the 2 pads per UART. */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure_pads(uart_gpios, 2);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #if ENV_RAMSTAGE</span><br><span> </span><br><span> void pch_uart_read_resources(struct device *dev)</span><br><span>diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c</span><br><span>index 1803694..34d3f7a 100644</span><br><span>--- a/src/soc/intel/skylake/bootblock/bootblock.c</span><br><span>+++ b/src/soc/intel/skylake/bootblock/bootblock.c</span><br><span>@@ -16,6 +16,7 @@</span><br><span> #include <bootblock_common.h></span><br><span> #include <drivers/i2c/designware/dw_i2c.h></span><br><span> #include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/uart.h></span><br><span> #include <soc/bootblock.h></span><br><span> </span><br><span> asmlinkage void bootblock_c_entry(uint64_t base_timestamp)</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h</span><br><span>index 59ce92a..f506514 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/bootblock.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/bootblock.h</span><br><span>@@ -27,7 +27,6 @@</span><br><span> /* Bootblock pre console init programming */</span><br><span> void bootblock_cpu_init(void);</span><br><span> void bootblock_pch_early_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_uart_init(void);</span><br><span> </span><br><span> /* Bootblock post console init programming */</span><br><span> void i2c_early_init(void);</span><br><span>diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c</span><br><span>index 945a0a0..703ed36 100644</span><br><span>--- a/src/soc/intel/skylake/uart.c</span><br><span>+++ b/src/soc/intel/skylake/uart.c</span><br><span>@@ -30,21 +30,23 @@</span><br><span> #define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))</span><br><span> </span><br><span> /* UART pad configuration. Support RXD and TXD for now. */</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pad_config uart_pads[][2] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config uart_gpios[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+struct pad_config *soc_get_gpio_pad(uint8_t pad_index)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((pad_index * 2) < sizeof(uart_gpios))</span><br><span style="color: hsl(120, 100%, 40%);">+ return &uart_gpios[pad_index * 2];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Invalid UART console index for soc");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)</span><br><span> uintptr_t uart_platform_base(int idx)</span><br><span> {</span><br><span>@@ -54,28 +56,6 @@</span><br><span> }</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void pch_uart_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- uart_common_init(pch_uart_get_device(), base);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Put UART in byte access mode for 16550 compatibility */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,</span><br><span style="color: hsl(0, 100%, 40%);">- PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Dummy read after setting any of GPPRVRW7.</span><br><span style="color: hsl(0, 100%, 40%);">- * Required for UART 16550 8-bit Legacy mode to become active</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- lpss_clk_read(base);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_configure_pads(uart_pads[CONFIG_UART_FOR_CONSOLE],</span><br><span style="color: hsl(0, 100%, 40%);">- ARRAY_SIZE(uart_pads[CONFIG_UART_FOR_CONSOLE]));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> device_t soc_uart_console_to_device(uint8_t uart_console)</span><br><span> {</span><br><span> /*</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26943">change 26943</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26943"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia583262d07e1c1ed2105fed25fbd5c8adb07c994 </div>
<div style="display:none"> Gerrit-Change-Number: 26943 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>