<p>Elyes HAOUAS <strong>uploaded patch set #7</strong> to this change.</p><p><a href="https://review.coreboot.org/26942">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">{arch,commonlib,cpu,device,drivers,lib,nb,sb}: Use "foo *bar" instead of "foo* bar"<br><br>Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/arch/x86/cpu.c<br>M src/commonlib/storage/mmc.c<br>M src/commonlib/storage/storage.c<br>M src/cpu/amd/pi/romstage.c<br>M src/cpu/intel/turbo/turbo.c<br>M src/cpu/via/nano/update_ucode.c<br>M src/device/device.c<br>M src/device/oprom/include/x86emu/regs.h<br>M src/device/oprom/yabel/compat/of.h<br>M src/device/oprom/yabel/debug.c<br>M src/device/oprom/yabel/debug.h<br>M src/device/oprom/yabel/vbe.c<br>M src/drivers/amd/agesa/oem_s3.c<br>M src/drivers/amd/agesa/state_machine.c<br>M src/drivers/aspeed/common/aspeed_coreboot.h<br>M src/drivers/i2c/tpm/tpm.c<br>M src/drivers/intel/fsp1_0/fsp_util.c<br>M src/drivers/intel/fsp1_0/fsp_util.h<br>M src/drivers/intel/fsp1_0/hob.c<br>M src/drivers/intel/gma/edid.c<br>M src/drivers/pc80/tpm/tis.c<br>M src/drivers/usb/ehci_debug.c<br>M src/drivers/usb/gadget.c<br>M src/drivers/xgi/common/xgi_coreboot.c<br>M src/lib/rtc.c<br>M src/northbridge/amd/amdht/h3gtopo.h<br>M src/northbridge/amd/amdht/ht_wrapper.c<br>M src/northbridge/amd/pi/agesawrapper.c<br>M src/northbridge/amd/pi/agesawrapper_call.h<br>M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c<br>M src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c<br>M src/northbridge/intel/gm45/iommu.c<br>M src/northbridge/intel/nehalem/raminit.c<br>M src/northbridge/intel/pineview/raminit.c<br>M src/northbridge/via/vx900/lpc.c<br>M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h<br>M src/southbridge/amd/cimx/sb800/Amd.h<br>M src/southbridge/amd/cimx/sb800/AmdSbLib.h<br>M src/southbridge/amd/cimx/sb800/amd_pci_int_types.h<br>M src/southbridge/amd/cimx/sb800/late.c<br>M src/southbridge/amd/cimx/sb900/Amd.h<br>M src/southbridge/amd/cimx/sb900/AmdSbLib.h<br>M src/southbridge/amd/cimx/sb900/amd_pci_int_types.h<br>M src/southbridge/amd/cimx/sb900/late.c<br>M src/southbridge/amd/common/amd_pci_util.c<br>M src/southbridge/amd/common/amd_pci_util.h<br>M src/southbridge/amd/pi/hudson/amd_pci_int_types.h<br>M src/southbridge/amd/pi/hudson/gpio.c<br>M src/southbridge/amd/rs780/gfx.c<br>M src/southbridge/amd/rs780/rs780.c<br>M src/southbridge/amd/sr5650/sr5650.c<br>51 files changed, 108 insertions(+), 102 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/26942/7</pre><p>To view, visit <a href="https://review.coreboot.org/26942">change 26942</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26942"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newpatchset </div>
<div style="display:none"> Gerrit-Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac </div>
<div style="display:none"> Gerrit-Change-Number: 26942 </div>
<div style="display:none"> Gerrit-PatchSet: 7 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>