<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26971">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/octopus: Fix GPIO to GPE mappings in devicetree<br><br>Change b41ae2 (mb/google/octopus: Enable wake-over-wifi for octopus<br>variants) changed the GPE mappings to accomodate for WiFi wake<br>pin. However, this resulted in TPM interrupt pin being removed from<br>the GPIO to GPE mapping. Since we do not support true interrupts in<br>coreboot, GPE_STS registers are used to identify if an interrupt has<br>triggered. Change in GPE mapping resulted in this information to be<br>lost when talking to TPM thus resulting in "Timeout wait for tpm<br>irq".<br><br>This change fixes the above issue by assigning GPIO block for TPM<br>interrupt back to DW1 and moving GPIO block for wake-over-wifi pin to<br>DW3. DW3 was mapping to NW_31_0 which only has debug header pins and<br>CNVI pins (none of them are used for reading GPE_STS or as wake<br>sources).<br><br>BUG=b:109824918<br>TEST=Verified that there are no "Timeout wait for tpm irq" messages<br>when talking to TPM.<br><br>Change-Id: I30768177a838a684948f7485d760c8b83c3190f7<br>Signed-off-by: Furquan Shaikh <furquan@google.com><br>---<br>M src/mainboard/google/octopus/variants/baseboard/devicetree.cb<br>M src/mainboard/google/octopus/variants/bip/devicetree.cb<br>2 files changed, 23 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/26971/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>index 9bd51ca..d6f0829 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>@@ -29,9 +29,18 @@</span><br><span> # route, i.e., if this route changes then the affected GPE</span><br><span> # offset bits also need to be changed. This sets the PMC register</span><br><span> # GPE_CFG fields.</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw1" = "PMC_GPE_N_63_32"</span><br><span style="color: hsl(120, 100%, 40%);">+ # DW1 is used by:</span><br><span style="color: hsl(120, 100%, 40%);">+ # - GPIO_63 - H1_PCH_INT_ODL</span><br><span style="color: hsl(120, 100%, 40%);">+ # DW2 is used by:</span><br><span style="color: hsl(120, 100%, 40%);">+ # - GPIO_141 - EC_PCH_WAKE_ODL</span><br><span style="color: hsl(120, 100%, 40%);">+ # - GPIO_142 - TRACKPAD_INT2_1V8_ODL</span><br><span style="color: hsl(120, 100%, 40%);">+ # - GPIO_144 - PEN_EJECT_ODL</span><br><span style="color: hsl(120, 100%, 40%);">+ # DW3 is used by:</span><br><span style="color: hsl(120, 100%, 40%);">+ # - GPIO_117 - LTE_WAKE_ODL</span><br><span style="color: hsl(120, 100%, 40%);">+ # - GPIO_119 - WLAN_PCIE_WAKE_ODL</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "PMC_GPE_NW_63_32"</span><br><span> register "gpe0_dw2" = "PMC_GPE_N_95_64"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw3" = "PMC_GPE_NW_31_0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw3" = "PMC_GPE_N_63_32"</span><br><span> </span><br><span> # PL1 override 8000 mW: Due to error in the energy calculation for</span><br><span> # current VR solution. Experiments show that SoC TDP max (6W) can</span><br><span>@@ -122,7 +131,7 @@</span><br><span> device pci 12.0 off end # - SATA</span><br><span> device pci 13.0 on</span><br><span> chip drivers/intel/wifi</span><br><span style="color: hsl(0, 100%, 40%);">- register "wake" = "GPE0_DW1_11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW3_11"</span><br><span> device pci 00.0 on end</span><br><span> end</span><br><span> end # - PCIe-A 0 Onboard M2 Slot(Wifi)</span><br><span>diff --git a/src/mainboard/google/octopus/variants/bip/devicetree.cb b/src/mainboard/google/octopus/variants/bip/devicetree.cb</span><br><span>index 339b5bf..8f2992b 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/bip/devicetree.cb</span><br><span>+++ b/src/mainboard/google/octopus/variants/bip/devicetree.cb</span><br><span>@@ -29,9 +29,17 @@</span><br><span> # route, i.e., if this route changes then the affected GPE</span><br><span> # offset bits also need to be changed. This sets the PMC register</span><br><span> # GPE_CFG fields.</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw1" = "PMC_GPE_N_63_32"</span><br><span style="color: hsl(120, 100%, 40%);">+ # DW1 is used by:</span><br><span style="color: hsl(120, 100%, 40%);">+ # - GPIO_63 - H1_PCH_INT_ODL</span><br><span style="color: hsl(120, 100%, 40%);">+ # DW2 is used by:</span><br><span style="color: hsl(120, 100%, 40%);">+ # - GPIO_141 - EC_PCH_WAKE_ODL</span><br><span style="color: hsl(120, 100%, 40%);">+ # - GPIO_142 - TRACKPAD_INT2_1V8_ODL</span><br><span style="color: hsl(120, 100%, 40%);">+ # DW3 is used by:</span><br><span style="color: hsl(120, 100%, 40%);">+ # - GPIO_117 - LTE_WAKE_ODL</span><br><span style="color: hsl(120, 100%, 40%);">+ # - GPIO_119 - WLAN_PCIE_WAKE_ODL</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "PMC_GPE_NW_63_32"</span><br><span> register "gpe0_dw2" = "PMC_GPE_N_95_64"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw3" = "PMC_GPE_NW_31_0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw3" = "PMC_GPE_N_63_32"</span><br><span> </span><br><span> # PL1 override 8000 mW: Due to error in the energy calculation for</span><br><span> # current VR solution. Experiments show that SoC TDP max (6W) can</span><br><span>@@ -122,7 +130,7 @@</span><br><span> device pci 12.0 off end # - SATA</span><br><span> device pci 13.0 on</span><br><span> chip drivers/intel/wifi</span><br><span style="color: hsl(0, 100%, 40%);">- register "wake" = "GPE0_DW1_11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW3_11"</span><br><span> device pci 00.0 on end</span><br><span> end</span><br><span> end # - PCIe-A 0 Onboard M2 Slot(Wifi)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26971">change 26971</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26971"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I30768177a838a684948f7485d760c8b83c3190f7 </div>
<div style="display:none"> Gerrit-Change-Number: 26971 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>