<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26942">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">{arch,commonlib,cpu,device,drivers,lib,nb,sb}: Use "foo *bar" instead of "foo* bar"<br><br>Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/arch/riscv/include/mcall.h<br>M src/arch/riscv/trap_handler.c<br>M src/arch/x86/cpu.c<br>M src/commonlib/lz4.c.inc<br>M src/commonlib/storage/mmc.c<br>M src/commonlib/storage/storage.c<br>M src/cpu/amd/family_10h-family_15h/init_cpus.c<br>M src/cpu/amd/pi/romstage.c<br>M src/cpu/intel/turbo/turbo.c<br>M src/cpu/via/nano/update_ucode.c<br>M src/device/device.c<br>M src/device/oprom/include/x86emu/regs.h<br>M src/device/oprom/yabel/compat/of.h<br>M src/device/oprom/yabel/debug.c<br>M src/device/oprom/yabel/debug.h<br>M src/device/oprom/yabel/vbe.c<br>M src/drivers/amd/agesa/oem_s3.c<br>M src/drivers/amd/agesa/state_machine.c<br>M src/drivers/aspeed/common/aspeed_coreboot.h<br>M src/drivers/i2c/tpm/tpm.c<br>M src/drivers/intel/fsp1_0/fsp_util.c<br>M src/drivers/intel/fsp1_0/fsp_util.h<br>M src/drivers/intel/fsp1_0/hob.c<br>M src/drivers/intel/gma/edid.c<br>M src/drivers/pc80/tpm/tis.c<br>M src/drivers/usb/ehci_debug.c<br>M src/drivers/usb/gadget.c<br>M src/drivers/xgi/common/xgi_coreboot.c<br>M src/lib/rtc.c<br>M src/northbridge/amd/amdht/h3gtopo.h<br>M src/northbridge/amd/amdht/ht_wrapper.c<br>M src/northbridge/amd/pi/agesawrapper.c<br>M src/northbridge/amd/pi/agesawrapper_call.h<br>M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c<br>M src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c<br>M src/northbridge/intel/gm45/iommu.c<br>M src/northbridge/intel/nehalem/raminit.c<br>M src/northbridge/intel/pineview/raminit.c<br>M src/northbridge/via/vx900/lpc.c<br>M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h<br>M src/southbridge/amd/cimx/sb800/Amd.h<br>M src/southbridge/amd/cimx/sb800/AmdSbLib.h<br>M src/southbridge/amd/cimx/sb800/amd_pci_int_types.h<br>M src/southbridge/amd/cimx/sb800/late.c<br>M src/southbridge/amd/cimx/sb900/Amd.h<br>M src/southbridge/amd/cimx/sb900/AmdSbLib.h<br>M src/southbridge/amd/cimx/sb900/amd_pci_int_types.h<br>M src/southbridge/amd/cimx/sb900/late.c<br>M src/southbridge/amd/common/amd_pci_util.c<br>M src/southbridge/amd/common/amd_pci_util.h<br>M src/southbridge/amd/pi/hudson/amd_pci_int_types.h<br>M src/southbridge/amd/pi/hudson/gpio.c<br>M src/southbridge/amd/rs780/gfx.c<br>M src/southbridge/amd/rs780/rs780.c<br>M src/southbridge/amd/sr5650/sr5650.c<br>55 files changed, 101 insertions(+), 101 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/26942/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h</span><br><span>index e4bc36f..56f2821 100644</span><br><span>--- a/src/arch/riscv/include/mcall.h</span><br><span>+++ b/src/arch/riscv/include/mcall.h</span><br><span>@@ -52,11 +52,11 @@</span><br><span> #define MACHINE_STACK_TOP() ({ \</span><br><span> /* coverity[uninit_use] : FALSE */ \</span><br><span> register uintptr_t sp asm ("sp"); \</span><br><span style="color: hsl(0, 100%, 40%);">- (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })</span><br><span style="color: hsl(120, 100%, 40%);">+ (void *)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })</span><br><span> </span><br><span> // hart-local storage, at top of stack</span><br><span> #define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE))</span><br><span style="color: hsl(0, 100%, 40%);">-#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id)))</span><br><span style="color: hsl(120, 100%, 40%);">+#define OTHER_HLS(id) ((hls_t*)((void *)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id)))</span><br><span> </span><br><span> #define MACHINE_STACK_SIZE RISCV_PGSIZE</span><br><span> </span><br><span>diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c</span><br><span>index 7b35c2e..1838a2b 100644</span><br><span>--- a/src/arch/riscv/trap_handler.c</span><br><span>+++ b/src/arch/riscv/trap_handler.c</span><br><span>@@ -74,8 +74,8 @@</span><br><span> previous_mode, mprv? " (MPRV)":"");</span><br><span> printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc);</span><br><span> printk(BIOS_DEBUG, "Bad address: %p\n", (void *)tf->badvaddr);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Stored ra: %p\n", (void*) tf->gpr[1]);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Stored ra: %p\n", (void *) tf->gpr[1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Stored sp: %p\n", (void *) tf->gpr[2]);</span><br><span> }</span><br><span> </span><br><span> static void gettimer(void)</span><br><span>@@ -201,7 +201,7 @@</span><br><span> printk(BIOS_DEBUG, "Width: %d bits\n", (1 << memWidth) * 8);</span><br><span> if (memWidth == 3) {</span><br><span> // load double, handle the issue</span><br><span style="color: hsl(0, 100%, 40%);">- void* badAddress = (void*) tf->badvaddr;</span><br><span style="color: hsl(120, 100%, 40%);">+ void * badAddress = (void *) tf->badvaddr;</span><br><span> uint64_t value = 0;</span><br><span> for (int i = 0; i < 8; i++) {</span><br><span> value <<= 8;</span><br><span>@@ -229,7 +229,7 @@</span><br><span> printk(BIOS_DEBUG, "Width: %d bits\n", (1 << memWidth) * 8);</span><br><span> if (memWidth == 3) {</span><br><span> // store double, handle the issue</span><br><span style="color: hsl(0, 100%, 40%);">- void* badAddress = (void*) tf->badvaddr;</span><br><span style="color: hsl(120, 100%, 40%);">+ void * badAddress = (void *) tf->badvaddr;</span><br><span> uint64_t value = tf->gpr[srcRegister];</span><br><span> for (int i = 0; i < 8; i++) {</span><br><span> mprv_write_u8(badAddress+i, value);</span><br><span>diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c</span><br><span>index 7a7c99b..6bbeb59 100644</span><br><span>--- a/src/arch/x86/cpu.c</span><br><span>+++ b/src/arch/x86/cpu.c</span><br><span>@@ -116,7 +116,7 @@</span><br><span> { X86_VENDOR_SIS, "SiS SiS SiS ", },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const x86_vendor_name[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const x86_vendor_name[] = {</span><br><span> [X86_VENDOR_INTEL] = "Intel",</span><br><span> [X86_VENDOR_CYRIX] = "Cyrix",</span><br><span> [X86_VENDOR_AMD] = "AMD",</span><br><span>diff --git a/src/commonlib/lz4.c.inc b/src/commonlib/lz4.c.inc</span><br><span>index b3be4e5..f25547d 100644</span><br><span>--- a/src/commonlib/lz4.c.inc</span><br><span>+++ b/src/commonlib/lz4.c.inc</span><br><span>@@ -38,14 +38,14 @@</span><br><span> **************************************/</span><br><span> </span><br><span> /* customized variant of memcpy, which can overwrite up to 7 bytes beyond dstEnd */</span><br><span style="color: hsl(0, 100%, 40%);">-static void LZ4_wildCopy(void* dstPtr, const void* srcPtr, void* dstEnd)</span><br><span style="color: hsl(120, 100%, 40%);">+static void LZ4_wildCopy(void * dstPtr, const void * srcPtr, void * dstEnd)</span><br><span> {</span><br><span> BYTE* d = (BYTE*)dstPtr;</span><br><span> const BYTE* s = (const BYTE*)srcPtr;</span><br><span> BYTE* const e = (BYTE*)dstEnd;</span><br><span> </span><br><span> #if 0</span><br><span style="color: hsl(0, 100%, 40%);">- const size_t l2 = 8 - (((size_t)d) & (sizeof(void*)-1));</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t l2 = 8 - (((size_t)d) & (sizeof(void *)-1));</span><br><span> LZ4_copy8(d,s); if (d>e-9) return;</span><br><span> d+=l2; s+=l2;</span><br><span> #endif /* join to align */</span><br><span>diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c</span><br><span>index d88e469..e09d826 100644</span><br><span>--- a/src/commonlib/storage/mmc.c</span><br><span>+++ b/src/commonlib/storage/mmc.c</span><br><span>@@ -529,7 +529,7 @@</span><br><span> const char *mmc_partition_name(struct storage_media *media,</span><br><span> unsigned int partition_number)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const partition_name[8] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const partition_name[8] = {</span><br><span> "User", /* 0 */</span><br><span> "Boot 1", /* 1 */</span><br><span> "Boot 2", /* 2 */</span><br><span>diff --git a/src/commonlib/storage/storage.c b/src/commonlib/storage/storage.c</span><br><span>index d2b566f..927e12f 100644</span><br><span>--- a/src/commonlib/storage/storage.c</span><br><span>+++ b/src/commonlib/storage/storage.c</span><br><span>@@ -31,7 +31,7 @@</span><br><span> #define HEX_CAPACITY_MULTIPLIER 1024ULL</span><br><span> </span><br><span> struct capacity {</span><br><span style="color: hsl(0, 100%, 40%);">- const char * const units;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *const units;</span><br><span> uint64_t bytes;</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c</span><br><span>index 0ecd040..bf9508a 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c</span><br><span>@@ -377,8 +377,8 @@</span><br><span> uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH;</span><br><span> uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE;</span><br><span> uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size;</span><br><span style="color: hsl(0, 100%, 40%);">- void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size);</span><br><span style="color: hsl(0, 100%, 40%);">- if (((void*)(sysinfo + 1)) > lower_stack_region_boundary)</span><br><span style="color: hsl(120, 100%, 40%);">+ void * lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - max_ap_stack_region_size);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (((void *)(sysinfo + 1)) > lower_stack_region_boundary)</span><br><span> printk(BIOS_WARNING,</span><br><span> "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n",</span><br><span> sysinfo, sysinfo + 1, lower_stack_region_boundary);</span><br><span>@@ -825,7 +825,7 @@</span><br><span> *</span><br><span> * Returns the offset of the link register.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset)</span><br><span style="color: hsl(120, 100%, 40%);">+static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset)</span><br><span> {</span><br><span> u32 reg;</span><br><span> u32 val;</span><br><span>diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c</span><br><span>index 9a5fbac..f4066e7 100644</span><br><span>--- a/src/cpu/amd/pi/romstage.c</span><br><span>+++ b/src/cpu/amd/pi/romstage.c</span><br><span>@@ -45,7 +45,7 @@</span><br><span> stack_top += HIGH_ROMSTAGE_STACK_SIZE;</span><br><span> </span><br><span> printk(BIOS_DEBUG, "Move CAR stack.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return (void*)stack_top;</span><br><span style="color: hsl(120, 100%, 40%);">+ return (void *)stack_top;</span><br><span> }</span><br><span> </span><br><span> void asmlinkage romstage_after_car(void)</span><br><span>diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c</span><br><span>index 9b93870..5583c46 100644</span><br><span>--- a/src/cpu/intel/turbo/turbo.c</span><br><span>+++ b/src/cpu/intel/turbo/turbo.c</span><br><span>@@ -42,7 +42,7 @@</span><br><span> }</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const turbo_state_desc[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const turbo_state_desc[] = {</span><br><span> [TURBO_UNKNOWN] = "unknown",</span><br><span> [TURBO_UNAVAILABLE] = "unavailable",</span><br><span> [TURBO_DISABLED] = "available but hidden",</span><br><span>diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c</span><br><span>index 9ff66e7..7c631a6 100644</span><br><span>--- a/src/cpu/via/nano/update_ucode.c</span><br><span>+++ b/src/cpu/via/nano/update_ucode.c</span><br><span>@@ -61,7 +61,7 @@</span><br><span> * Two's complement done over the entire file, including the header */</span><br><span> int i;</span><br><span> u32 check = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 *raw = (void*) ucode;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *raw = (void *) ucode;</span><br><span> for (i = 0; i < ((ucode->total_size) >> 2); i++) {</span><br><span> check += raw[i];</span><br><span> }</span><br><span>diff --git a/src/device/device.c b/src/device/device.c</span><br><span>index 79dceaa..7ba9d0a 100644</span><br><span>--- a/src/device/device.c</span><br><span>+++ b/src/device/device.c</span><br><span>@@ -195,7 +195,7 @@</span><br><span> return val;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const char * resource2str(struct resource *res)</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *resource2str(struct resource *res)</span><br><span> {</span><br><span> if (res->flags & IORESOURCE_IO)</span><br><span> return "io";</span><br><span>diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h</span><br><span>index 8eec112..e0908c1 100644</span><br><span>--- a/src/device/oprom/include/x86emu/regs.h</span><br><span>+++ b/src/device/oprom/include/x86emu/regs.h</span><br><span>@@ -306,7 +306,7 @@</span><br><span> unsigned long mem_base;</span><br><span> unsigned long mem_size;</span><br><span> unsigned long abseg;</span><br><span style="color: hsl(0, 100%, 40%);">- void* private;</span><br><span style="color: hsl(120, 100%, 40%);">+ void * private;</span><br><span> X86EMU_regs x86;</span><br><span> } X86EMU_sysEnv;</span><br><span> </span><br><span>diff --git a/src/device/oprom/yabel/compat/of.h b/src/device/oprom/yabel/compat/of.h</span><br><span>index 31c9b59..8224c78 100644</span><br><span>--- a/src/device/oprom/yabel/compat/of.h</span><br><span>+++ b/src/device/oprom/yabel/compat/of.h</span><br><span>@@ -35,7 +35,7 @@</span><br><span> #ifndef OF_H</span><br><span> #define OF_H</span><br><span> #define p32 int</span><br><span style="color: hsl(0, 100%, 40%);">-#define p32cast (int) (unsigned long) (void*)</span><br><span style="color: hsl(120, 100%, 40%);">+#define p32cast (int) (unsigned long) (void *)</span><br><span> </span><br><span> #define phandle_t p32</span><br><span> #define ihandle_t p32</span><br><span>@@ -59,8 +59,8 @@</span><br><span> </span><br><span> ihandle_t of_open (const char *);</span><br><span> void of_close(ihandle_t);</span><br><span style="color: hsl(0, 100%, 40%);">-int of_read (ihandle_t , void*, int);</span><br><span style="color: hsl(0, 100%, 40%);">-int of_write (ihandle_t, void*, int);</span><br><span style="color: hsl(120, 100%, 40%);">+int of_read (ihandle_t , void *, int);</span><br><span style="color: hsl(120, 100%, 40%);">+int of_write (ihandle_t, void *, int);</span><br><span> int of_seek (ihandle_t, int, int);</span><br><span> </span><br><span> void * of_claim(void *, unsigned int , unsigned int );</span><br><span>diff --git a/src/device/oprom/yabel/debug.c b/src/device/oprom/yabel/debug.c</span><br><span>index daa263e..fc226fe 100644</span><br><span>--- a/src/device/oprom/yabel/debug.c</span><br><span>+++ b/src/device/oprom/yabel/debug.c</span><br><span>@@ -37,7 +37,7 @@</span><br><span> u32 debug_flags = 0;</span><br><span> </span><br><span> void</span><br><span style="color: hsl(0, 100%, 40%);">-dump(u8 * addr, u32 len)</span><br><span style="color: hsl(120, 100%, 40%);">+dump(u8 *addr, u32 len)</span><br><span> {</span><br><span> printf("\n%s(%p, %x):\n", __func__, addr, len);</span><br><span> while (len) {</span><br><span>diff --git a/src/device/oprom/yabel/debug.h b/src/device/oprom/yabel/debug.h</span><br><span>index b1a8600..20db261 100644</span><br><span>--- a/src/device/oprom/yabel/debug.h</span><br><span>+++ b/src/device/oprom/yabel/debug.h</span><br><span>@@ -130,6 +130,6 @@</span><br><span> </span><br><span> #endif //DEBUG</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void dump(u8 * addr, u32 len);</span><br><span style="color: hsl(120, 100%, 40%);">+void dump(u8 *addr, u32 len);</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c</span><br><span>index 5402ddf..c8b99d5 100644</span><br><span>--- a/src/device/oprom/yabel/vbe.c</span><br><span>+++ b/src/device/oprom/yabel/vbe.c</span><br><span>@@ -321,7 +321,7 @@</span><br><span> }</span><br><span> </span><br><span> static u8</span><br><span style="color: hsl(0, 100%, 40%);">-vbe_get_color(u16 color_number, u32 * color_value)</span><br><span style="color: hsl(120, 100%, 40%);">+vbe_get_color(u16 color_number, u32 *color_value)</span><br><span> {</span><br><span> vbe_prepare();</span><br><span> // call VBE function 09h (Set/Get Palette Data Function)</span><br><span>diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c</span><br><span>index 1ca6e5b..ad193e1 100644</span><br><span>--- a/src/drivers/amd/agesa/oem_s3.c</span><br><span>+++ b/src/drivers/amd/agesa/oem_s3.c</span><br><span>@@ -161,5 +161,5 @@</span><br><span> if (!size)</span><br><span> return NULL;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- return (void*)(pos + sizeof(UINT32));</span><br><span style="color: hsl(120, 100%, 40%);">+ return (void *)(pos + sizeof(UINT32));</span><br><span> }</span><br><span>diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c</span><br><span>index b73c124..673bf9b 100644</span><br><span>--- a/src/drivers/amd/agesa/state_machine.c</span><br><span>+++ b/src/drivers/amd/agesa/state_machine.c</span><br><span>@@ -53,7 +53,7 @@</span><br><span> </span><br><span> image = LibAmdLocateImage(agesa, agesa + file_size, 4096,</span><br><span> ModuleIdentifier);</span><br><span style="color: hsl(0, 100%, 40%);">- StdHeader->ImageBasePtr = (void*) image;</span><br><span style="color: hsl(120, 100%, 40%);">+ StdHeader->ImageBasePtr = (void *) image;</span><br><span> #endif</span><br><span> }</span><br><span> </span><br><span>@@ -66,10 +66,10 @@</span><br><span> if (IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI)) {</span><br><span> agesa_locate_image(&cb->StdHeader);</span><br><span> AMD_IMAGE_HEADER *image =</span><br><span style="color: hsl(0, 100%, 40%);">- (void*)(uintptr_t)cb->StdHeader.ImageBasePtr;</span><br><span style="color: hsl(120, 100%, 40%);">+ (void *)(uintptr_t)cb->StdHeader.ImageBasePtr;</span><br><span> ASSERT(image);</span><br><span> AMD_MODULE_HEADER *module =</span><br><span style="color: hsl(0, 100%, 40%);">- (void*)(uintptr_t)image->ModuleInfoOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+ (void *)(uintptr_t)image->ModuleInfoOffset;</span><br><span> ASSERT(module && module->ModuleDispatcher);</span><br><span> }</span><br><span> }</span><br><span>@@ -83,8 +83,8 @@</span><br><span> dispatcher = AmdAgesaDispatcher;</span><br><span> #endif</span><br><span> #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI)</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_IMAGE_HEADER *image = (void*)(uintptr_t)StdHeader->ImageBasePtr;</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_MODULE_HEADER *module = (void*)(uintptr_t)image->ModuleInfoOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_IMAGE_HEADER *image = (void *)(uintptr_t)StdHeader->ImageBasePtr;</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_MODULE_HEADER *module = (void *)(uintptr_t)image->ModuleInfoOffset;</span><br><span> dispatcher = module->ModuleDispatcher;</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/drivers/aspeed/common/aspeed_coreboot.h b/src/drivers/aspeed/common/aspeed_coreboot.h</span><br><span>index 5a208e6..544e8e8 100644</span><br><span>--- a/src/drivers/aspeed/common/aspeed_coreboot.h</span><br><span>+++ b/src/drivers/aspeed/common/aspeed_coreboot.h</span><br><span>@@ -73,7 +73,7 @@</span><br><span> };</span><br><span> </span><br><span> static inline void *kzalloc(size_t size, int flags) {</span><br><span style="color: hsl(0, 100%, 40%);">- void* ptr = malloc(size);</span><br><span style="color: hsl(120, 100%, 40%);">+ void * ptr = malloc(size);</span><br><span> memset(ptr, 0, size);</span><br><span> return ptr;</span><br><span> }</span><br><span>diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c</span><br><span>index 7d69861..447fc24 100644</span><br><span>--- a/src/drivers/i2c/tpm/tpm.c</span><br><span>+++ b/src/drivers/i2c/tpm/tpm.c</span><br><span>@@ -65,7 +65,7 @@</span><br><span> UNKNOWN,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const chip_name[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const chip_name[] = {</span><br><span> [SLB9635] = "slb9635tt",</span><br><span> [SLB9645] = "slb9645tt",</span><br><span> [UNKNOWN] = "unknown/fallback to slb9635",</span><br><span>diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c</span><br><span>index 5a6321d..8880fbd 100644</span><br><span>--- a/src/drivers/intel/fsp1_0/fsp_util.c</span><br><span>+++ b/src/drivers/intel/fsp1_0/fsp_util.c</span><br><span>@@ -75,7 +75,7 @@</span><br><span> UPD_DATA_REGION fsp_upd_data;</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));</span><br><span style="color: hsl(120, 100%, 40%);">+ memset((void *)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));</span><br><span> FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP;</span><br><span> FspInitParams.NvsBufferPtr = NULL;</span><br><span> </span><br><span>@@ -100,7 +100,7 @@</span><br><span> }</span><br><span> #endif /* __PRE_RAM__ */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-volatile u8 * find_fsp ()</span><br><span style="color: hsl(120, 100%, 40%);">+volatile u8 *find_fsp ()</span><br><span> {</span><br><span> </span><br><span> #ifdef __PRE_RAM__</span><br><span>@@ -221,7 +221,7 @@</span><br><span> }</span><br><span> </span><br><span> if (FspHobListPtr == NULL) {</span><br><span style="color: hsl(0, 100%, 40%);">- FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));</span><br><span style="color: hsl(120, 100%, 40%);">+ FspHobListPtr = (void *)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));</span><br><span> }</span><br><span> </span><br><span> printk(BIOS_SPEW,"fsp_header_ptr: %p\n", fsp_header_ptr);</span><br><span>@@ -294,7 +294,7 @@</span><br><span> static void find_fsp_hob_update_mrc(void *unused)</span><br><span> {</span><br><span> /* Set the global HOB list pointer */</span><br><span style="color: hsl(0, 100%, 40%);">- FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));</span><br><span style="color: hsl(120, 100%, 40%);">+ FspHobListPtr = (void *)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));</span><br><span> </span><br><span> if (!FspHobListPtr){</span><br><span> printk(BIOS_ERR, "ERROR: Could not find FSP HOB pointer in CBFS!\n");</span><br><span>diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h</span><br><span>index a3a7dd3..b53ece0 100644</span><br><span>--- a/src/drivers/intel/fsp1_0/fsp_util.h</span><br><span>+++ b/src/drivers/intel/fsp1_0/fsp_util.h</span><br><span>@@ -25,7 +25,7 @@</span><br><span> void * find_and_set_fastboot_cache(void);</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-volatile u8 * find_fsp(void);</span><br><span style="color: hsl(120, 100%, 40%);">+volatile u8 *find_fsp(void);</span><br><span> void fsp_early_init(FSP_INFO_HEADER *fsp_info);</span><br><span> void FspNotify(u32 Phase);</span><br><span> void FspNotifyReturnPoint(EFI_STATUS Status, VOID *HobListPtr);</span><br><span>@@ -42,7 +42,7 @@</span><br><span> void print_hob_type_structure(u16 Hobtype, void *Hoblistptr);</span><br><span> void print_hob_resource_attributes(void *Hobptr);</span><br><span> void print_guid_type_attributes(void *Hobptr);</span><br><span style="color: hsl(0, 100%, 40%);">-const char * get_hob_type_string(void *Hobptr);</span><br><span style="color: hsl(120, 100%, 40%);">+const char *get_hob_type_string(void *Hobptr);</span><br><span> void * find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1);</span><br><span> uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2);</span><br><span> void printguid(EFI_GUID *guid);</span><br><span>diff --git a/src/drivers/intel/fsp1_0/hob.c b/src/drivers/intel/fsp1_0/hob.c</span><br><span>index 4aac147..83d5543 100644</span><br><span>--- a/src/drivers/intel/fsp1_0/hob.c</span><br><span>+++ b/src/drivers/intel/fsp1_0/hob.c</span><br><span>@@ -42,7 +42,7 @@</span><br><span> EFI_MEMORY_TYPE Hobmemtype = HobMemoryPtr->AllocDescriptor.MemoryType;</span><br><span> u64 Hobmemaddr = HobMemoryPtr->AllocDescriptor.MemoryBaseAddress;</span><br><span> u64 Hobmemlength = HobMemoryPtr->AllocDescriptor.MemoryLength;</span><br><span style="color: hsl(0, 100%, 40%);">- const char * Hobmemtypenames[15];</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *Hobmemtypenames[15];</span><br><span> </span><br><span> Hobmemtypenames[0] = "EfiReservedMemoryType";</span><br><span> Hobmemtypenames[1] = "EfiLoaderCode";</span><br><span>@@ -104,7 +104,7 @@</span><br><span> (unsigned long)Hobresaddr, (unsigned long)Hobreslength);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const char * get_hob_type_string(void *Hobptr)</span><br><span style="color: hsl(120, 100%, 40%);">+const char *get_hob_type_string(void *Hobptr)</span><br><span> {</span><br><span> EFI_HOB_GENERIC_HEADER *HobHeaderPtr = (EFI_HOB_GENERIC_HEADER *)Hobptr;</span><br><span> u16 Hobtype = HobHeaderPtr->HobType;</span><br><span>diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c</span><br><span>index 316e869..13b301f 100644</span><br><span>--- a/src/drivers/intel/gma/edid.c</span><br><span>+++ b/src/drivers/intel/gma/edid.c</span><br><span>@@ -39,7 +39,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_gmbus_stop_bus(u8 * mmio, u8 bus)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_gmbus_stop_bus(u8 *mmio, u8 bus)</span><br><span> {</span><br><span> wait_rdy(mmio);</span><br><span> write32(GMBUS0_ADDR, bus);</span><br><span>diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c</span><br><span>index 3549173..bd1033d 100644</span><br><span>--- a/src/drivers/pc80/tpm/tis.c</span><br><span>+++ b/src/drivers/pc80/tpm/tis.c</span><br><span>@@ -109,12 +109,12 @@</span><br><span> */</span><br><span> struct device_name {</span><br><span> u16 dev_id;</span><br><span style="color: hsl(0, 100%, 40%);">- const char * const dev_name;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *const dev_name;</span><br><span> };</span><br><span> </span><br><span> struct vendor_name {</span><br><span> u16 vendor_id;</span><br><span style="color: hsl(0, 100%, 40%);">- const char * vendor_name;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *vendor_name;</span><br><span> const struct device_name* dev_names;</span><br><span> };</span><br><span> </span><br><span>@@ -443,7 +443,7 @@</span><br><span> * Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does</span><br><span> * not accept the entire command).</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 tis_senddata(const u8 * const data, u32 len)</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 tis_senddata(const u8 *const data, u32 len)</span><br><span> {</span><br><span> u32 offset = 0;</span><br><span> u16 burst = 0;</span><br><span>diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c</span><br><span>index fcc5223..52b4bdd 100644</span><br><span>--- a/src/drivers/usb/ehci_debug.c</span><br><span>+++ b/src/drivers/usb/ehci_debug.c</span><br><span>@@ -631,7 +631,7 @@</span><br><span> </span><br><span> diff = (unsigned)dbg_info->ehci_base - ehci_base;</span><br><span> dbg_info->ehci_debug -= diff;</span><br><span style="color: hsl(0, 100%, 40%);">- dbg_info->ehci_base = (void*)ehci_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ dbg_info->ehci_base = (void *)ehci_base;</span><br><span> </span><br><span> for (i=0; i<DBGP_MAX_ENDPOINTS; i++)</span><br><span> if (dbg_info->ep_pipe[i].status & DBGP_EP_VALID)</span><br><span>diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c</span><br><span>index 37e97a3..3254a8a 100644</span><br><span>--- a/src/drivers/usb/gadget.c</span><br><span>+++ b/src/drivers/usb/gadget.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> #define USB_HUB_C_PORT_RESET 20</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int hub_port_status(const char * buf, int feature)</span><br><span style="color: hsl(120, 100%, 40%);">+static int hub_port_status(const char *buf, int feature)</span><br><span> {</span><br><span> return !!(buf[feature>>3] & (1<<(feature&0x7)));</span><br><span> }</span><br><span>diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c</span><br><span>index 9cd634c..cee7dfb 100644</span><br><span>--- a/src/drivers/xgi/common/xgi_coreboot.c</span><br><span>+++ b/src/drivers/xgi/common/xgi_coreboot.c</span><br><span>@@ -130,8 +130,8 @@</span><br><span> </span><br><span> hw_info->ulVideoMemorySize = xgifb_info->video_size;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- xgifb_info->video_vbase = hw_info->pjVideoMemoryAddress = (void*)(intptr_t)xgifb_info->video_base;</span><br><span style="color: hsl(0, 100%, 40%);">- xgifb_info->mmio_vbase = (void*)(intptr_t)xgifb_info->mmio_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ xgifb_info->video_vbase = hw_info->pjVideoMemoryAddress = (void *)(intptr_t)xgifb_info->video_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ xgifb_info->mmio_vbase = (void *)(intptr_t)xgifb_info->mmio_base;</span><br><span> </span><br><span> dev_info(&pdev->dev,</span><br><span> "Framebuffer at 0x%Lx, mapped to 0x%p, size %dk\n",</span><br><span>diff --git a/src/lib/rtc.c b/src/lib/rtc.c</span><br><span>index bd98590..c5c157f 100644</span><br><span>--- a/src/lib/rtc.c</span><br><span>+++ b/src/lib/rtc.c</span><br><span>@@ -31,7 +31,7 @@</span><br><span> 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const weekdays[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const weekdays[] = {</span><br><span> "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur",</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/northbridge/amd/amdht/h3gtopo.h b/src/northbridge/amd/amdht/h3gtopo.h</span><br><span>index 58673aa..ca14816 100644</span><br><span>--- a/src/northbridge/amd/amdht/h3gtopo.h</span><br><span>+++ b/src/northbridge/amd/amdht/h3gtopo.h</span><br><span>@@ -324,7 +324,7 @@</span><br><span> 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x65, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const u8 * const amd_topo_list[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const u8 *const amd_topo_list[] = {</span><br><span> amdHtTopologySingleNode,</span><br><span> amdHtTopologyDualNode,</span><br><span> amdHtTopologyThreeLine,</span><br><span>diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c</span><br><span>index f4e8337..5e33325 100644</span><br><span>--- a/src/northbridge/amd/amdht/ht_wrapper.c</span><br><span>+++ b/src/northbridge/amd/amdht/ht_wrapper.c</span><br><span>@@ -55,7 +55,7 @@</span><br><span> *----------------------------------------------------------------------------</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const char * event_class_string_decodes[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *event_class_string_decodes[] = {</span><br><span> [HT_EVENT_CLASS_CRITICAL] = "CRITICAL",</span><br><span> [HT_EVENT_CLASS_ERROR] = "ERROR",</span><br><span> [HT_EVENT_CLASS_HW_FAULT] = "HARDWARE FAULT",</span><br><span>@@ -65,7 +65,7 @@</span><br><span> </span><br><span> typedef struct {</span><br><span> uint32_t code;</span><br><span style="color: hsl(0, 100%, 40%);">- const char * string;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *string;</span><br><span> } event_string_decode_t;</span><br><span> </span><br><span> static const event_string_decode_t event_string_decodes[] = {</span><br><span>@@ -90,7 +90,7 @@</span><br><span> { HT_EVENT_HW_HTCRC, "HT_EVENT_HW_HTCRC" }</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const char * event_string_decode(uint32_t event) {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *event_string_decode(uint32_t event) {</span><br><span> uint32_t i;</span><br><span> for (i = 0; i < ARRAY_SIZE(event_string_decodes); i++)</span><br><span> if (event_string_decodes[i].code == event)</span><br><span>diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c</span><br><span>index a66917b..c8578f6 100644</span><br><span>--- a/src/northbridge/amd/pi/agesawrapper.c</span><br><span>+++ b/src/northbridge/amd/pi/agesawrapper.c</span><br><span>@@ -289,7 +289,7 @@</span><br><span> </span><br><span> const void *agesawrapper_locate_module (const CHAR8 name[8])</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- const void* agesa;</span><br><span style="color: hsl(120, 100%, 40%);">+ const void * agesa;</span><br><span> const AMD_IMAGE_HEADER* image;</span><br><span> const AMD_MODULE_HEADER* module;</span><br><span> size_t file_size;</span><br><span>diff --git a/src/northbridge/amd/pi/agesawrapper_call.h b/src/northbridge/amd/pi/agesawrapper_call.h</span><br><span>index 1ed4a4c..bfcd78d 100644</span><br><span>--- a/src/northbridge/amd/pi/agesawrapper_call.h</span><br><span>+++ b/src/northbridge/amd/pi/agesawrapper_call.h</span><br><span>@@ -30,7 +30,7 @@</span><br><span> * 0x6 = AGESA_CRITICAL</span><br><span> * 0x7 = AGESA_FATAL</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static const char * decodeAGESA_STATUS(AGESA_STATUS sret)</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *decodeAGESA_STATUS(AGESA_STATUS sret)</span><br><span> {</span><br><span> const char *statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",</span><br><span> "AGESA_BOUNDS_CHK", "AGESA_ALERT",</span><br><span>diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c</span><br><span>index ed79f45..999d5a8 100644</span><br><span>--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c</span><br><span>+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c</span><br><span>@@ -43,7 +43,7 @@</span><br><span> + FspInfo->ImageBase);</span><br><span> UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)</span><br><span> (VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));</span><br><span> }</span><br><span> </span><br><span> typedef struct northbridge_intel_fsp_rangeley_config config_t;</span><br><span>diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c</span><br><span>index 888da8e..eb31655 100644</span><br><span>--- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c</span><br><span>+++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c</span><br><span>@@ -33,7 +33,7 @@</span><br><span> UPD_DATA_REGION *UpdDataRgnPtr;</span><br><span> VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase);</span><br><span> UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));</span><br><span> }</span><br><span> </span><br><span> static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)</span><br><span>@@ -70,7 +70,7 @@</span><br><span> UPD_DATA_REGION *fsp_upd_data = pFspRtBuffer->Common.UpdDataRgnPtr;</span><br><span> #else</span><br><span> MEM_CONFIG MemoryConfig;</span><br><span style="color: hsl(0, 100%, 40%);">- memset((void*)&MemoryConfig, 0, sizeof(MEM_CONFIG));</span><br><span style="color: hsl(120, 100%, 40%);">+ memset((void *)&MemoryConfig, 0, sizeof(MEM_CONFIG));</span><br><span> #endif</span><br><span> FspInitParams->NvsBufferPtr = NULL;</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c</span><br><span>index 77aba94..0a4a017 100644</span><br><span>--- a/src/northbridge/intel/gm45/iommu.c</span><br><span>+++ b/src/northbridge/intel/gm45/iommu.c</span><br><span>@@ -54,7 +54,7 @@</span><br><span> u8 cmd = pci_read_config8(igd, PCI_COMMAND);</span><br><span> cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;</span><br><span> pci_write_config8(igd, PCI_COMMAND, cmd);</span><br><span style="color: hsl(0, 100%, 40%);">- void* bar = (void*)pci_read_config32(igd, PCI_BASE_ADDRESS_0);</span><br><span style="color: hsl(120, 100%, 40%);">+ void * bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0);</span><br><span> </span><br><span> /* clear GTT, 2MB is enough (and should be safe) */</span><br><span> memset(bar, 0, 2<<20);</span><br><span>diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c</span><br><span>index 6a27b57..f68031b 100644</span><br><span>--- a/src/northbridge/intel/nehalem/raminit.c</span><br><span>+++ b/src/northbridge/intel/nehalem/raminit.c</span><br><span>@@ -1787,7 +1787,7 @@</span><br><span> csr.csr.buffer_read_ptr));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void send_heci_packet(struct mei_header *head, u32 * payload)</span><br><span style="color: hsl(120, 100%, 40%);">+static void send_heci_packet(struct mei_header *head, u32 *payload)</span><br><span> {</span><br><span> int len = (head->length + 3) / 4;</span><br><span> int i;</span><br><span>@@ -1804,7 +1804,7 @@</span><br><span> }</span><br><span> </span><br><span> static void</span><br><span style="color: hsl(0, 100%, 40%);">-send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress)</span><br><span style="color: hsl(120, 100%, 40%);">+send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress)</span><br><span> {</span><br><span> struct mei_header head;</span><br><span> int maxlen;</span><br><span>@@ -1831,8 +1831,8 @@</span><br><span> </span><br><span> /* FIXME: Add timeout. */</span><br><span> static int</span><br><span style="color: hsl(0, 100%, 40%);">-recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,</span><br><span style="color: hsl(0, 100%, 40%);">- u32 * packet_size)</span><br><span style="color: hsl(120, 100%, 40%);">+recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 *packet,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *packet_size)</span><br><span> {</span><br><span> union {</span><br><span> struct mei_csr csr;</span><br><span>@@ -1878,7 +1878,7 @@</span><br><span> </span><br><span> /* FIXME: Add timeout. */</span><br><span> static int</span><br><span style="color: hsl(0, 100%, 40%);">-recv_heci_message(struct raminfo *info, u32 * message, u32 * message_size)</span><br><span style="color: hsl(120, 100%, 40%);">+recv_heci_message(struct raminfo *info, u32 *message, u32 *message_size)</span><br><span> {</span><br><span> struct mei_header head;</span><br><span> int current_position;</span><br><span>@@ -2292,9 +2292,9 @@</span><br><span> }</span><br><span> </span><br><span> static void</span><br><span style="color: hsl(0, 100%, 40%);">-do_fsm(enum state *state, u16 * counter,</span><br><span style="color: hsl(120, 100%, 40%);">+do_fsm(enum state *state, u16 *counter,</span><br><span> u8 fail_mask, int margin, int uplimit,</span><br><span style="color: hsl(0, 100%, 40%);">- u8 * res_low, u8 * res_high, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *res_low, u8 *res_high, u8 val)</span><br><span> {</span><br><span> int lane;</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c</span><br><span>index f31f032..66f0a10 100644</span><br><span>--- a/src/northbridge/intel/pineview/raminit.c</span><br><span>+++ b/src/northbridge/intel/pineview/raminit.c</span><br><span>@@ -1845,7 +1845,7 @@</span><br><span> MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2;</span><br><span> hpet_udelay(1);</span><br><span> barrier();</span><br><span style="color: hsl(0, 100%, 40%);">- strobedata = read32((void*)strobeaddr);</span><br><span style="color: hsl(120, 100%, 40%);">+ strobedata = read32((void *)strobeaddr);</span><br><span> barrier();</span><br><span> hpet_udelay(1);</span><br><span> </span><br><span>diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c</span><br><span>index 075a872..b90e2d4 100644</span><br><span>--- a/src/northbridge/via/vx900/lpc.c</span><br><span>+++ b/src/northbridge/via/vx900/lpc.c</span><br><span>@@ -246,7 +246,7 @@</span><br><span> };</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_PIRQ_ROUTE)</span><br><span style="color: hsl(0, 100%, 40%);">-void pirq_assign_irqs(const u8 * pirq)</span><br><span style="color: hsl(120, 100%, 40%);">+void pirq_assign_irqs(const u8 *pirq)</span><br><span> {</span><br><span> struct device *lpc;</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h</span><br><span>index 7b74561..328818c 100644</span><br><span>--- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h</span><br><span>+++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h</span><br><span>@@ -17,7 +17,7 @@</span><br><span> #define AMD_PCI_INT_TYPES_H</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)</span><br><span style="color: hsl(0, 100%, 40%);">-const char * intr_types[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const char *intr_types[] = {</span><br><span> [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",</span><br><span> [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",</span><br><span> [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t",</span><br><span>@@ -27,7 +27,7 @@</span><br><span> [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t"</span><br><span> };</span><br><span> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)</span><br><span style="color: hsl(0, 100%, 40%);">-const char * intr_types[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const char *intr_types[] = {</span><br><span> [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",</span><br><span> [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",</span><br><span> [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t",</span><br><span>diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h</span><br><span>index 42e2b3a..879b95c 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb800/Amd.h</span><br><span>+++ b/src/southbridge/amd/cimx/sb800/Amd.h</span><br><span>@@ -61,9 +61,9 @@</span><br><span> #define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002)</span><br><span> #define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr);</span><br><span style="color: hsl(0, 100%, 40%);">-typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr);</span><br><span style="color: hsl(0, 100%, 40%);">-typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);</span><br><span style="color: hsl(120, 100%, 40%);">+typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void * ConfigPtr);</span><br><span style="color: hsl(120, 100%, 40%);">+typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void * ConfigPtr);</span><br><span style="color: hsl(120, 100%, 40%);">+typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void * ConfigPtr);</span><br><span> </span><br><span> ///This allocation type is used by the AmdCreateStruct entry point</span><br><span> typedef enum {</span><br><span>diff --git a/src/southbridge/amd/cimx/sb800/AmdSbLib.h b/src/southbridge/amd/cimx/sb800/AmdSbLib.h</span><br><span>index c13eda4..6210c50 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb800/AmdSbLib.h</span><br><span>+++ b/src/southbridge/amd/cimx/sb800/AmdSbLib.h</span><br><span>@@ -28,7 +28,7 @@</span><br><span> #define NUM_IMAGE_LOCATION 32</span><br><span> </span><br><span> //Entry Point Call</span><br><span style="color: hsl(0, 100%, 40%);">-typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);</span><br><span style="color: hsl(120, 100%, 40%);">+typedef void (*CIM_IMAGE_ENTRY) (void * pConfig);</span><br><span> </span><br><span> //Hook Call</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h</span><br><span>index 854f9c3..300969d 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h</span><br><span>+++ b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h</span><br><span>@@ -16,7 +16,7 @@</span><br><span> #ifndef AMD_PCI_INT_TYPES_H</span><br><span> #define AMD_PCI_INT_TYPES_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const char * intr_types[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const char *intr_types[] = {</span><br><span> [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",</span><br><span> [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",</span><br><span> [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t",</span><br><span>diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c</span><br><span>index ebc6ba1..9cc48f9 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb800/late.c</span><br><span>+++ b/src/southbridge/amd/cimx/sb800/late.c</span><br><span>@@ -43,14 +43,14 @@</span><br><span> /**</span><br><span> * @brief Entry point of Southbridge CIMx callout</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)</span><br><span style="color: hsl(120, 100%, 40%);">+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void * pConfig)</span><br><span> *</span><br><span> * @param[in] func Southbridge CIMx Function ID.</span><br><span> * @param[in] data Southbridge Input Data.</span><br><span> * @param[in] config Southbridge configuration structure pointer.</span><br><span> *</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 sb800_callout_entry(u32 func, u32 data, void* config)</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 sb800_callout_entry(u32 func, u32 data, void * config)</span><br><span> {</span><br><span> u32 ret = 0;</span><br><span> printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);</span><br><span>diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h</span><br><span>index ec81400..c92ebac 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb900/Amd.h</span><br><span>+++ b/src/southbridge/amd/cimx/sb900/Amd.h</span><br><span>@@ -61,9 +61,9 @@</span><br><span> #define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002)</span><br><span> #define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr);</span><br><span style="color: hsl(0, 100%, 40%);">-typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr);</span><br><span style="color: hsl(0, 100%, 40%);">-typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);</span><br><span style="color: hsl(120, 100%, 40%);">+typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void * ConfigPtr);</span><br><span style="color: hsl(120, 100%, 40%);">+typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void * ConfigPtr);</span><br><span style="color: hsl(120, 100%, 40%);">+typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void * ConfigPtr);</span><br><span> </span><br><span> ///This allocation type is used by the AmdCreateStruct entry point</span><br><span> typedef enum {</span><br><span>diff --git a/src/southbridge/amd/cimx/sb900/AmdSbLib.h b/src/southbridge/amd/cimx/sb900/AmdSbLib.h</span><br><span>index c13eda4..6210c50 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb900/AmdSbLib.h</span><br><span>+++ b/src/southbridge/amd/cimx/sb900/AmdSbLib.h</span><br><span>@@ -28,7 +28,7 @@</span><br><span> #define NUM_IMAGE_LOCATION 32</span><br><span> </span><br><span> //Entry Point Call</span><br><span style="color: hsl(0, 100%, 40%);">-typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);</span><br><span style="color: hsl(120, 100%, 40%);">+typedef void (*CIM_IMAGE_ENTRY) (void * pConfig);</span><br><span> </span><br><span> //Hook Call</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h</span><br><span>index 854f9c3..300969d 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h</span><br><span>+++ b/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h</span><br><span>@@ -16,7 +16,7 @@</span><br><span> #ifndef AMD_PCI_INT_TYPES_H</span><br><span> #define AMD_PCI_INT_TYPES_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const char * intr_types[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const char *intr_types[] = {</span><br><span> [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",</span><br><span> [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",</span><br><span> [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t",</span><br><span>diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c</span><br><span>index e792fe3..7b35543 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb900/late.c</span><br><span>+++ b/src/southbridge/amd/cimx/sb900/late.c</span><br><span>@@ -38,14 +38,14 @@</span><br><span> /**</span><br><span> * @brief Entry point of Southbridge CIMx callout</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)</span><br><span style="color: hsl(120, 100%, 40%);">+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void * pConfig)</span><br><span> *</span><br><span> * @param[in] func Southbridge CIMx Function ID.</span><br><span> * @param[in] data Southbridge Input Data.</span><br><span> * @param[in] config Southbridge configuration structure pointer.</span><br><span> *</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-u32 sb900_callout_entry(u32 func, u32 data, void* config)</span><br><span style="color: hsl(120, 100%, 40%);">+u32 sb900_callout_entry(u32 func, u32 data, void * config)</span><br><span> {</span><br><span> u32 ret = 0;</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c</span><br><span>index 2acd151..ca76809 100644</span><br><span>--- a/src/southbridge/amd/common/amd_pci_util.c</span><br><span>+++ b/src/southbridge/amd/common/amd_pci_util.c</span><br><span>@@ -26,8 +26,8 @@</span><br><span> </span><br><span> const struct pirq_struct * pirq_data_ptr = NULL;</span><br><span> u32 pirq_data_size = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-const u8 * intr_data_ptr = NULL;</span><br><span style="color: hsl(0, 100%, 40%);">-const u8 * picr_data_ptr = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+const u8 *intr_data_ptr = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+const u8 *picr_data_ptr = NULL;</span><br><span> </span><br><span> /*</span><br><span> * Read the FCH PCI_INTR registers 0xC00/0xC01 at a</span><br><span>diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h</span><br><span>index 452db65..9a4695e 100644</span><br><span>--- a/src/southbridge/amd/common/amd_pci_util.h</span><br><span>+++ b/src/southbridge/amd/common/amd_pci_util.h</span><br><span>@@ -32,8 +32,8 @@</span><br><span> </span><br><span> extern const struct pirq_struct * pirq_data_ptr;</span><br><span> extern u32 pirq_data_size;</span><br><span style="color: hsl(0, 100%, 40%);">-extern const u8 * intr_data_ptr;</span><br><span style="color: hsl(0, 100%, 40%);">-extern const u8 * picr_data_ptr;</span><br><span style="color: hsl(120, 100%, 40%);">+extern const u8 *intr_data_ptr;</span><br><span style="color: hsl(120, 100%, 40%);">+extern const u8 *picr_data_ptr;</span><br><span> </span><br><span> u8 read_pci_int_idx(u8 index, int mode);</span><br><span> void write_pci_int_idx(u8 index, int mode, u8 data);</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h</span><br><span>index f898907..8061bf7 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h</span><br><span>+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h</span><br><span>@@ -16,7 +16,7 @@</span><br><span> #ifndef AMD_PCI_INT_TYPES_H</span><br><span> #define AMD_PCI_INT_TYPES_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const char * intr_types[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const char *intr_types[] = {</span><br><span> [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",</span><br><span> [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",</span><br><span> [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t\t",</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/gpio.c b/src/southbridge/amd/pi/hudson/gpio.c</span><br><span>index 5b2eb4c..d3e5cfa 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/gpio.c</span><br><span>+++ b/src/southbridge/amd/pi/hudson/gpio.c</span><br><span>@@ -22,7 +22,7 @@</span><br><span> {</span><br><span> uint32_t reg;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- reg = read32((void*)(uintptr_t)gpio_num);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = read32((void *)(uintptr_t)gpio_num);</span><br><span> </span><br><span> return !!(reg & GPIO_PIN_STS);</span><br><span> }</span><br><span>diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c</span><br><span>index cfcddb2..9497934 100644</span><br><span>--- a/src/southbridge/amd/rs780/gfx.c</span><br><span>+++ b/src/southbridge/amd/rs780/gfx.c</span><br><span>@@ -311,9 +311,9 @@</span><br><span> </span><br><span> static void internal_gfx_pci_dev_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char * bpointer;</span><br><span style="color: hsl(0, 100%, 40%);">- volatile u32 * GpuF0MMReg;</span><br><span style="color: hsl(0, 100%, 40%);">- volatile u32 * pointer;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned char *bpointer;</span><br><span style="color: hsl(120, 100%, 40%);">+ volatile u32 *GpuF0MMReg;</span><br><span style="color: hsl(120, 100%, 40%);">+ volatile u32 *pointer;</span><br><span> int i;</span><br><span> u16 command;</span><br><span> u32 value;</span><br><span>diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c</span><br><span>index ef40ffd..457cdf3 100644</span><br><span>--- a/src/southbridge/amd/rs780/rs780.c</span><br><span>+++ b/src/southbridge/amd/rs780/rs780.c</span><br><span>@@ -187,7 +187,7 @@</span><br><span> {</span><br><span> /* NB_InitGFXStraps */</span><br><span> u32 MMIOBase, apc04, apc18, apc24, romstrap2;</span><br><span style="color: hsl(0, 100%, 40%);">- volatile u32 * strap;</span><br><span style="color: hsl(120, 100%, 40%);">+ volatile u32 *strap;</span><br><span> </span><br><span> /* Choose a base address that is unused and routed to the RS780. */</span><br><span> MMIOBase = 0xFFB00000;</span><br><span>diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c</span><br><span>index 1962ea3..8eb4bc6 100644</span><br><span>--- a/src/southbridge/amd/sr5650/sr5650.c</span><br><span>+++ b/src/southbridge/amd/sr5650/sr5650.c</span><br><span>@@ -336,7 +336,7 @@</span><br><span> return;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- mmio_base = (void*)(pci_read_config32(iommu_dev, 0x44) & 0xffffc000);</span><br><span style="color: hsl(120, 100%, 40%);">+ mmio_base = (void *)(pci_read_config32(iommu_dev, 0x44) & 0xffffc000);</span><br><span> </span><br><span> // if (get_nb_rev(nb_dev) == REV_SR5650_A11) {</span><br><span> // dword = pci_read_config32(iommu_dev, 0x6c);</span><br><span>@@ -352,11 +352,11 @@</span><br><span> dword |= 0x1;</span><br><span> pci_write_config32(iommu_dev, 0x44, dword);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32((void*)(mmio_base + 0x8), 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32((void*)(mmio_base + 0xc), 0x08000000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32((void*)(mmio_base + 0x10), 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32((void*)(mmio_base + 0x2008), 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32((void*)(mmio_base + 0x2010), 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((void *)(mmio_base + 0x8), 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((void *)(mmio_base + 0xc), 0x08000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((void *)(mmio_base + 0x10), 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((void *)(mmio_base + 0x2008), 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((void *)(mmio_base + 0x2010), 0x0);</span><br><span> </span><br><span> /* IOMMU L1 initialization */</span><br><span> for (l1_target = 0; l1_target < 6; l1_target++) {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26942">change 26942</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26942"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac </div>
<div style="display:none"> Gerrit-Change-Number: 26942 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>