<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26882">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/{apollolake, geminilake}: Rectify GSPI device name<br><br>As per GLK EDS B:D:F (0:0xd:2) is HW SEQ SPI and (0:0x19:0-2) are GSPI0-2<br><br>Change-Id: Iff540eefa5e93b8ad86916745705b48e99cc6767<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/apollolake/include/soc/pci_devs.h<br>M src/soc/intel/apollolake/spi.c<br>2 files changed, 12 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/26882/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h</span><br><span>index 25b74ba..c715c4f 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/pci_devs.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h</span><br><span>@@ -131,13 +131,13 @@</span><br><span> #define PCH_DEV_UART3 _PCH_DEV(UART, 3)</span><br><span> </span><br><span> /* LPSS SPI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEV_SLOT_SPI 0x19</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEVFN_SPI0 _PCH_DEVFN(SPI, 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEVFN_SPI1 _PCH_DEVFN(SPI, 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEVFN_SPI2 _PCH_DEVFN(SPI, 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEV_SPI0 _PCH_DEV(SPI, 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEV_SPI1 _PCH_DEV(SPI, 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEV_SPI2 _PCH_DEV(SPI, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_GSPI 0x19</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_GSPI0 _PCH_DEVFN(GSPI, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_GSPI1 _PCH_DEVFN(GSPI, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_GSPI2 _PCH_DEVFN(GSPI, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_GSPI0 _PCH_DEV(GSPI, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_GSPI1 _PCH_DEV(GSPI, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_GSPI2 _PCH_DEV(GSPI, 2)</span><br><span> </span><br><span> /* LPSS PWM */</span><br><span> #define PCH_DEV_SLOT_PWM 0x1a</span><br><span>diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c</span><br><span>index b85d6b1..ecc2e32 100644</span><br><span>--- a/src/soc/intel/apollolake/spi.c</span><br><span>+++ b/src/soc/intel/apollolake/spi.c</span><br><span>@@ -21,12 +21,14 @@</span><br><span> int spi_soc_devfn_to_bus(unsigned int devfn)</span><br><span> {</span><br><span> switch (devfn) {</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_SPI0:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEV_SPI:</span><br><span> return 0;</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_SPI1:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_GSPI0:</span><br><span> return 1;</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_SPI2:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_GSPI1:</span><br><span> return 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_GSPI2:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 3;</span><br><span> }</span><br><span> return -1;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26882">change 26882</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26882"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iff540eefa5e93b8ad86916745705b48e99cc6767 </div>
<div style="display:none"> Gerrit-Change-Number: 26882 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>