<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26880">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek: Refine whitespace and formating changes<br><br>This patch fix whitespace and formating issues:<br>1. Using two spaces between code and single line comment.<br>2. No space after asterisk.<br>3. Fix checkpatch error<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=the refactored code works fine on the new platform (with the rest<br> of the patches applied) and Elm platform<br><br>Change-Id: Ib36c99b141c94220776fab606eb36af8f64f65bb<br>Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com><br>---<br>M src/soc/mediatek/mt8173/dramc_pi_basic_api.c<br>M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c<br>M src/soc/mediatek/mt8173/include/soc/ddp.h<br>M src/soc/mediatek/mt8173/include/soc/dsi.h<br>M src/soc/mediatek/mt8173/include/soc/flash_controller.h<br>M src/soc/mediatek/mt8173/include/soc/mcucfg.h<br>M src/soc/mediatek/mt8173/include/soc/pericfg.h<br>M src/soc/mediatek/mt8173/include/soc/pmic_wrap.h<br>M src/soc/mediatek/mt8173/include/soc/spm.h<br>M src/soc/mediatek/mt8173/include/soc/timer.h<br>M src/soc/mediatek/mt8173/include/soc/usb.h<br>M src/soc/mediatek/mt8173/mt6391.c<br>M src/soc/mediatek/mt8173/pll.c<br>M src/soc/mediatek/mt8173/pmic_wrap.c<br>M src/soc/mediatek/mt8173/rtc.c<br>M src/soc/mediatek/mt8173/uart.c<br>M src/soc/mediatek/mt8173/wdt.c<br>17 files changed, 51 insertions(+), 49 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/26880/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c</span><br><span>index 83ba999..e471b4f 100644</span><br><span>--- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c</span><br><span>+++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c</span><br><span>@@ -264,7 +264,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- udelay(20); /* delay 20us for external loop pll stable */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(20); /* delay 20us for external loop pll stable */</span><br><span> </span><br><span> /* 2. enable mempll 2 3 4 jitter meter */</span><br><span> for (i = 0; i < 3; i++)</span><br><span>@@ -323,7 +323,7 @@</span><br><span> for (channel = 0; channel < CHANNEL_NUM; channel++)</span><br><span> mem_pll_init_set_params(channel);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- udelay(1); /* wait after da_mpll_sdm_iso_en goes low */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1); /* wait after da_mpll_sdm_iso_en goes low */</span><br><span> </span><br><span> /* only set once in MPLL */</span><br><span> mt_mem_pll_config_post();</span><br><span>@@ -391,7 +391,7 @@</span><br><span> /* unrequest mempll reset/pdn mode and wait settle */</span><br><span> clrbits_le32(&mt8173_spm->power_on_val0, 0x1 << 27);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- udelay(31); /* PLL ready */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(31); /* PLL ready */</span><br><span> </span><br><span> for (channel = 0; channel < CHANNEL_NUM; channel++)</span><br><span> mem_pll_init_phase_sync(channel);</span><br><span>@@ -402,7 +402,7 @@</span><br><span> for (channel = 0; channel < CHANNEL_NUM; channel++)</span><br><span> mem_pll_phase_cali(channel);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- div2_phase_sync(); /* phase sync for channel B */</span><br><span style="color: hsl(120, 100%, 40%);">+ div2_phase_sync(); /* phase sync for channel B */</span><br><span> </span><br><span> mt_mem_pll_mux();</span><br><span> }</span><br><span>@@ -584,7 +584,7 @@</span><br><span> write32(&ch[channel].ao_regs->padctl4, 0x1 << 2 |</span><br><span> 0x1 << 0);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- udelay(200); /* tINIT3 > 200us */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(200); /* tINIT3 > 200us */</span><br><span> </span><br><span> write32(&ch[channel].ao_regs->gddr3ctl1, 0x1 << 24 |</span><br><span> 0x1 << 20);</span><br><span>@@ -682,7 +682,7 @@</span><br><span> setbits_le32(&ch[channel].ao_regs->gddr3ctl1,</span><br><span> 1 << GDDR3CTL1_RDATRST_SHIFT);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- udelay(1); /* delay 1ns */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1); /* delay 1ns */</span><br><span> </span><br><span> clrbits_le32(&ch[channel].ao_regs->gddr3ctl1,</span><br><span> 1 << GDDR3CTL1_RDATRST_SHIFT);</span><br><span>diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c</span><br><span>index e77ec7c..2e2f0e6 100644</span><br><span>--- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c</span><br><span>+++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c</span><br><span>@@ -37,7 +37,7 @@</span><br><span> dramc_dbg_msg("[Imp Calibration] DRVP:%d\n", params->impedance_drvp);</span><br><span> dramc_dbg_msg("[Imp Calibration] DRVN:%d\n", params->impedance_drvn);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- mask = 0xf << 28 | 0xf << 24 | 0xf << 12 | 0xf << 8; /* driving */</span><br><span style="color: hsl(120, 100%, 40%);">+ mask = 0xf << 28 | 0xf << 24 | 0xf << 12 | 0xf << 8; /* driving */</span><br><span> </span><br><span> value = params->impedance_drvp << 28 | params->impedance_drvn << 24 |</span><br><span> params->impedance_drvp << 12 | params->impedance_drvn << 8;</span><br><span>@@ -201,7 +201,7 @@</span><br><span> coarse_tune_start = 15;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- curr_val_p1 = curr_val + 2; /* diff is 0.5T */</span><br><span style="color: hsl(120, 100%, 40%);">+ curr_val_p1 = curr_val + 2; /* diff is 0.5T */</span><br><span> </span><br><span> /* Rank 0 P0/P1 coarse tune settings */</span><br><span> clrsetbits_le32(&ch[channel].ao_regs->dqsctl1,</span><br><span>@@ -248,7 +248,7 @@</span><br><span> {</span><br><span> u8 curr_val_p1, r1dqsgate, r1dqsgate_p1;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- curr_val_p1 = curr_val + 2; /* diff is 0.5T */</span><br><span style="color: hsl(120, 100%, 40%);">+ curr_val_p1 = curr_val + 2; /* diff is 0.5T */</span><br><span> </span><br><span> clrsetbits_le32(&ch[channel].ao_regs->dqsctl2,</span><br><span> 0xf << DQSCTL2_DQSINCTL_SHIFT,</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/ddp.h b/src/soc/mediatek/mt8173/include/soc/ddp.h</span><br><span>index 20e356a..db2500a 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/ddp.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/ddp.h</span><br><span>@@ -142,7 +142,7 @@</span><br><span> </span><br><span> check_member(mmsys_cfg_regs, mmsys_sw1_rst_b, 0x144);</span><br><span> check_member(mmsys_cfg_regs, hdmi_en, 0x904);</span><br><span style="color: hsl(0, 100%, 40%);">-static struct mmsys_cfg_regs * const mmsys_cfg = (void *) MMSYS_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mmsys_cfg_regs *const mmsys_cfg = (void *) MMSYS_BASE;</span><br><span> </span><br><span> /* DISP_REG_CONFIG_MMSYS_CG_CON0</span><br><span> Configures free-run clock gating 0</span><br><span>@@ -240,7 +240,7 @@</span><br><span> };</span><br><span> </span><br><span> check_member(disp_mutex_regs, debug_out_sel, 0x100);</span><br><span style="color: hsl(0, 100%, 40%);">-static struct disp_mutex_regs * const disp_mutex = (void *) DISP_MUTEX_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct disp_mutex_regs *const disp_mutex = (void *) DISP_MUTEX_BASE;</span><br><span> </span><br><span> enum {</span><br><span> MUTEX_MOD_DISP_OVL0 = BIT(11),</span><br><span>@@ -306,7 +306,7 @@</span><br><span> };</span><br><span> </span><br><span> check_member(disp_ovl_regs, l3_addr, 0xFA0);</span><br><span style="color: hsl(0, 100%, 40%);">-static struct disp_ovl_regs * const disp_ovl[2] =</span><br><span style="color: hsl(120, 100%, 40%);">+static struct disp_ovl_regs *const disp_ovl[2] =</span><br><span> {(void *) DIS_OVL0_BASE, (void *) DIS_OVL1_BASE};</span><br><span> </span><br><span> struct disp_rdma_regs {</span><br><span>@@ -341,7 +341,7 @@</span><br><span> };</span><br><span> </span><br><span> check_member(disp_rdma_regs, debug_out_sel, 0x94);</span><br><span style="color: hsl(0, 100%, 40%);">-static struct disp_rdma_regs * const disp_rdma[3] =</span><br><span style="color: hsl(120, 100%, 40%);">+static struct disp_rdma_regs *const disp_rdma[3] =</span><br><span> {(void *)DISP_RDMA0_BASE, (void *)DISP_RDMA1_BASE, (void *)DISP_RDMA2_BASE};</span><br><span> </span><br><span> struct disp_od_regs {</span><br><span>@@ -363,7 +363,7 @@</span><br><span> };</span><br><span> </span><br><span> check_member(disp_od_regs, misc, 0x48);</span><br><span style="color: hsl(0, 100%, 40%);">-static struct disp_od_regs * const disp_od = (void *)DISP_OD_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct disp_od_regs *const disp_od = (void *)DISP_OD_BASE;</span><br><span> </span><br><span> enum {</span><br><span> OD_RELAY_MODE = BIT(0),</span><br><span>@@ -396,7 +396,7 @@</span><br><span> };</span><br><span> </span><br><span> check_member(disp_ufoe_regs, dbg[7], 0x15C);</span><br><span style="color: hsl(0, 100%, 40%);">-static struct disp_ufoe_regs * const disp_ufoe = (void *)DISP_UFOE_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct disp_ufoe_regs *const disp_ufoe = (void *)DISP_UFOE_BASE;</span><br><span> </span><br><span> enum {</span><br><span> UFO_BYPASS = BIT(2),</span><br><span>@@ -407,7 +407,7 @@</span><br><span> u32 start;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct disp_split_regs * const disp_split = (void *)DISP_SPLIT1_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct disp_split_regs *const disp_split = (void *)DISP_SPLIT1_BASE;</span><br><span> </span><br><span> struct disp_color_regs {</span><br><span> u8 reserved0[1024];</span><br><span>@@ -423,7 +423,7 @@</span><br><span> check_member(disp_color_regs, start, 0xC00);</span><br><span> check_member(disp_color_regs, width, 0xC50);</span><br><span> check_member(disp_color_regs, height, 0xC54);</span><br><span style="color: hsl(0, 100%, 40%);">-static struct disp_color_regs * const disp_color[2] =</span><br><span style="color: hsl(120, 100%, 40%);">+static struct disp_color_regs *const disp_color[2] =</span><br><span> {(void *)DISP_COLOR0_BASE, (void *)DISP_COLOR1_BASE};</span><br><span> </span><br><span> enum {</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h</span><br><span>index 68f45d1..ca35bd1 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/dsi.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/dsi.h</span><br><span>@@ -91,8 +91,8 @@</span><br><span> check_member(dsi_regs, dsi_phy_timecon3, 0x11c);</span><br><span> check_member(dsi_regs, dsi_vm_cmd_con, 0x130);</span><br><span> check_member(dsi_regs, dsi_cmdq0, 0x200);</span><br><span style="color: hsl(0, 100%, 40%);">-static struct dsi_regs * const dsi0 = (void *)DSI0_BASE;</span><br><span style="color: hsl(0, 100%, 40%);">-static struct dsi_regs * const dsi1 = (void *)DSI1_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct dsi_regs *const dsi1 = (void *)DSI1_BASE;</span><br><span> </span><br><span> /* DSI_INTSTA */</span><br><span> enum {</span><br><span>@@ -227,8 +227,8 @@</span><br><span> check_member(mipi_tx_regs, dsi_top_con, 0x40);</span><br><span> check_member(mipi_tx_regs, dsi_pll_pwr, 0x68);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct mipi_tx_regs * const mipi_tx0 = (void *)MIPI_TX0_BASE;</span><br><span style="color: hsl(0, 100%, 40%);">-static struct mipi_tx_regs * const mipi_tx1 = (void *)MIPI_TX0_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPI_TX0_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPI_TX0_BASE;</span><br><span> </span><br><span> /* MIPITX_DSI0_CON */</span><br><span> enum {</span><br><span>@@ -322,8 +322,8 @@</span><br><span> u32 vopll_ctl3;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct lvds_tx1_regs * const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800);</span><br><span style="color: hsl(0, 100%, 40%);">-static struct lvds_tx1_regs * const lvds_tx2 = (void *)(MIPI_TX1_BASE + 0x800);</span><br><span style="color: hsl(120, 100%, 40%);">+static struct lvds_tx1_regs *const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800);</span><br><span style="color: hsl(120, 100%, 40%);">+static struct lvds_tx1_regs *const lvds_tx2 = (void *)(MIPI_TX1_BASE + 0x800);</span><br><span> </span><br><span> /* LVDS_VOPLL_CTRL3 */</span><br><span> enum {</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/flash_controller.h b/src/soc/mediatek/mt8173/include/soc/flash_controller.h</span><br><span>index 82d167a..da306c5 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/flash_controller.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/flash_controller.h</span><br><span>@@ -85,7 +85,7 @@</span><br><span> u32 fdma_end_dadr;</span><br><span> };</span><br><span> check_member(mt8173_nor_regs, fdma_end_dadr, 0x724);</span><br><span style="color: hsl(0, 100%, 40%);">-static struct mt8173_nor_regs * const mt8173_nor = (void *)SFLASH_REG_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8173_nor_regs *const mt8173_nor = (void *)SFLASH_REG_BASE;</span><br><span> </span><br><span> int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash);</span><br><span> </span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/mcucfg.h b/src/soc/mediatek/mt8173/include/soc/mcucfg.h</span><br><span>index c8749d3..5c01150 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/mcucfg.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/mcucfg.h</span><br><span>@@ -102,6 +102,6 @@</span><br><span> </span><br><span> check_member(mt8173_mcucfg_regs, mcusys_rw_rsvd1, 0x688);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct mt8173_mcucfg_regs * const mt8173_mcucfg = (void *)MCUCFG_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE;</span><br><span> </span><br><span> #endif /* __SOC_MEDIATEK_MT8173_MCUCFG_H__ */</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/pericfg.h b/src/soc/mediatek/mt8173/include/soc/pericfg.h</span><br><span>index 8e3e477..5aa8542 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/pericfg.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/pericfg.h</span><br><span>@@ -78,7 +78,7 @@</span><br><span> u32 ssusb_pdn_sta;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct mt8173_pericfg_regs * const mt8173_pericfg =</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8173_pericfg_regs *const mt8173_pericfg =</span><br><span> (void *)PERI_CON_BASE;</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h</span><br><span>index 7861b69..6807b13 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h</span><br><span>@@ -25,7 +25,7 @@</span><br><span> s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check);</span><br><span> s32 pwrap_init(void);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct mt8173_pwrap_regs * const mt8173_pwrap = (void *)PMIC_WRAP_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8173_pwrap_regs *const mt8173_pwrap = (void *)PMIC_WRAP_BASE;</span><br><span> </span><br><span> enum {</span><br><span> WACS2 = 1 << 4</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h</span><br><span>index 9c23562..77516fc 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/spm.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/spm.h</span><br><span>@@ -154,6 +154,6 @@</span><br><span> </span><br><span> check_member(mt8173_spm_regs, sleep_ca15_wfi_en[3], 0xf1c);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct mt8173_spm_regs * const mt8173_spm = (void *)SPM_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8173_spm_regs *const mt8173_spm = (void *)SPM_BASE;</span><br><span> </span><br><span> #endif /* __SOC_MEDIATEK_MT8173_SPM_H__ */</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/timer.h b/src/soc/mediatek/mt8173/include/soc/timer.h</span><br><span>index ac2f00f..39aacb4 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/timer.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/timer.h</span><br><span>@@ -55,7 +55,7 @@</span><br><span> u32 apxgpt_irqmask1;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct mt8173_gpt_regs * const mt8173_gpt = (void *)GPT_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8173_gpt_regs *const mt8173_gpt = (void *)GPT_BASE;</span><br><span> </span><br><span> enum {</span><br><span> GPT_CON_EN = 0x01,</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/usb.h b/src/soc/mediatek/mt8173/include/soc/usb.h</span><br><span>index 915e247..646b077 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/usb.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/usb.h</span><br><span>@@ -134,7 +134,7 @@</span><br><span> u32 reserved1[17];</span><br><span> u32 u2phydtm0;</span><br><span> u32 u2phydtm1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved2[36]; /* 0x70 - 0xff */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved2[36]; /* 0x70 - 0xff */</span><br><span> };</span><br><span> check_member(sif_u2_phy_com, u2phydtm0, 0x68);</span><br><span> </span><br><span>diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c</span><br><span>index 2338aae..4f6ba32 100644</span><br><span>--- a/src/soc/mediatek/mt8173/mt6391.c</span><br><span>+++ b/src/soc/mediatek/mt8173/mt6391.c</span><br><span>@@ -152,7 +152,7 @@</span><br><span> mt6391_write(PMIC_RG_VCA15_CON7, 0x1, 0x1, 0);</span><br><span> mt6391_write(PMIC_RG_VSRMCA15_CON7, 0x1, 0x1, 0);</span><br><span> mt6391_write(PMIC_RG_VPCA7_CON7, 0x1, 0x1, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- udelay(200); /* delay for Buck ready */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(200); /* delay for Buck ready */</span><br><span> </span><br><span> /* [3:3]: RG_PWMOC_CK_PDN; For OC protection */</span><br><span> mt6391_write(PMIC_RG_TOP_CKPDN, 0x0, 0x1, 3);</span><br><span>diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c</span><br><span>index 1366bb5..d95f769 100644</span><br><span>--- a/src/soc/mediatek/mt8173/pll.c</span><br><span>+++ b/src/soc/mediatek/mt8173/pll.c</span><br><span>@@ -328,7 +328,7 @@</span><br><span> for (i = 0; i < APMIXED_NR_PLL; i++)</span><br><span> setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us) */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us) */</span><br><span> </span><br><span> /******************</span><br><span> * xPLL ISO Disable</span><br><span>@@ -361,7 +361,7 @@</span><br><span> for (i = 0; i < APMIXED_NR_PLL; i++)</span><br><span> setbits_le32(plls[i].reg, PLL_EN);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- udelay(40); /* wait for PLL stable (min delay is 20us) */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(40); /* wait for PLL stable (min delay is 20us) */</span><br><span> </span><br><span> /***************</span><br><span> * xPLL DIV RSTB</span><br><span>@@ -448,12 +448,12 @@</span><br><span> {</span><br><span> /* set RG_LTECLKSQ_EN */</span><br><span> setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1);</span><br><span style="color: hsl(0, 100%, 40%);">- udelay(100); /* wait for PLL stable */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(100); /* wait for PLL stable */</span><br><span> </span><br><span> /* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */</span><br><span> setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1 << 1);</span><br><span> setbits_le32(&mt8173_apmixed->ap_pll_con2, 0x1);</span><br><span style="color: hsl(0, 100%, 40%);">- udelay(100); /* wait for PLL stable */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(100); /* wait for PLL stable */</span><br><span> </span><br><span> /* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */</span><br><span> setbits_le32(&mt8173_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1));</span><br><span>diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c</span><br><span>index f4f2e37..d7d4193 100644</span><br><span>--- a/src/soc/mediatek/mt8173/pmic_wrap.c</span><br><span>+++ b/src/soc/mediatek/mt8173/pmic_wrap.c</span><br><span>@@ -88,7 +88,7 @@</span><br><span> return E_PWR_WAIT_IDLE_TIMEOUT;</span><br><span> </span><br><span> } while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=</span><br><span style="color: hsl(0, 100%, 40%);">- WACS_FSM_IDLE); /* IDLE State */</span><br><span style="color: hsl(120, 100%, 40%);">+ WACS_FSM_IDLE); /* IDLE State */</span><br><span> if (read_reg)</span><br><span> *read_reg = reg_rdata;</span><br><span> return 0;</span><br><span>@@ -108,7 +108,7 @@</span><br><span> pwrap_err("timeout when waiting for idle\n");</span><br><span> return E_PWR_WAIT_IDLE_TIMEOUT;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- } while (fp(reg_rdata)); /* IDLE State */</span><br><span style="color: hsl(120, 100%, 40%);">+ } while (fp(reg_rdata)); /* IDLE State */</span><br><span> if (read_reg)</span><br><span> *read_reg = reg_rdata;</span><br><span> return 0;</span><br><span>diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c</span><br><span>index 4147a0f..4d2cad4 100644</span><br><span>--- a/src/soc/mediatek/mt8173/rtc.c</span><br><span>+++ b/src/soc/mediatek/mt8173/rtc.c</span><br><span>@@ -127,7 +127,7 @@</span><br><span> if (!write_trigger())</span><br><span> return 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pwrap_read(RTC_IRQ_STA, &irqsta); /* read clear */</span><br><span style="color: hsl(120, 100%, 40%);">+ pwrap_read(RTC_IRQ_STA, &irqsta); /* read clear */</span><br><span> </span><br><span> /* init time counters after resetting RTC_DIFF and RTC_CALI */</span><br><span> pwrap_write(RTC_TC_YEA, RTC_DEFAULT_YEA - RTC_MIN_YEAR);</span><br><span>@@ -147,7 +147,7 @@</span><br><span> u16 con;</span><br><span> </span><br><span> mt6391_gpio_set_pull(3, MT6391_GPIO_PULL_DISABLE,</span><br><span style="color: hsl(0, 100%, 40%);">- MT6391_GPIO_PULL_DOWN); /* RTC_32K1V8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MT6391_GPIO_PULL_DOWN); /* RTC_32K1V8 */</span><br><span> </span><br><span> /* Export 32K clock RTC_32K2V8 */</span><br><span> pwrap_read(RTC_CON, &con);</span><br><span>@@ -307,7 +307,7 @@</span><br><span> break;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pwrap_read(RTC_IRQ_STA, &irqsta); /* Read clear */</span><br><span style="color: hsl(120, 100%, 40%);">+ pwrap_read(RTC_IRQ_STA, &irqsta); /* Read clear */</span><br><span> pwrap_read(RTC_BBPU, &bbpu);</span><br><span> pwrap_read(RTC_CON, &con);</span><br><span> </span><br><span>diff --git a/src/soc/mediatek/mt8173/uart.c b/src/soc/mediatek/mt8173/uart.c</span><br><span>index 93625c4..cfc469b 100644</span><br><span>--- a/src/soc/mediatek/mt8173/uart.c</span><br><span>+++ b/src/soc/mediatek/mt8173/uart.c</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2015 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -86,10 +86,10 @@</span><br><span> static void mtk_uart_init(void)</span><br><span> {</span><br><span> /* Use a hardcoded divisor for now. */</span><br><span style="color: hsl(0, 100%, 40%);">- const unsigned uartclk = 26 * MHz;</span><br><span style="color: hsl(0, 100%, 40%);">- const unsigned baudrate = get_uart_baudrate();</span><br><span style="color: hsl(0, 100%, 40%);">- const uint8_t line_config = UART8250_LCR_WLS_8; /* 8n1 */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned highspeed, quot, divisor, remainder;</span><br><span style="color: hsl(120, 100%, 40%);">+ const unsigned int uartclk = 26 * MHz;</span><br><span style="color: hsl(120, 100%, 40%);">+ const unsigned int baudrate = get_uart_baudrate();</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint8_t line_config = UART8250_LCR_WLS_8; /* 8n1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int highspeed, quot, divisor, remainder;</span><br><span> </span><br><span> if (baudrate <= 115200) {</span><br><span> highspeed = 0;</span><br><span>@@ -124,19 +124,21 @@</span><br><span> /* Enable FIFOs, and clear receive and transmit. */</span><br><span> write8(&uart_ptr->fcr,</span><br><span> UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR |</span><br><span style="color: hsl(0, 100%, 40%);">- UART8250_FCR_CLEAR_XMIT);</span><br><span style="color: hsl(120, 100%, 40%);">+ UART8250_FCR_CLEAR_XMIT);</span><br><span> </span><br><span> }</span><br><span> </span><br><span> static void mtk_uart_tx_byte(unsigned char data)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));</span><br><span style="color: hsl(120, 100%, 40%);">+ while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE))</span><br><span style="color: hsl(120, 100%, 40%);">+ ;</span><br><span> write8(&uart_ptr->thr, data);</span><br><span> }</span><br><span> </span><br><span> static void mtk_uart_tx_flush(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT));</span><br><span style="color: hsl(120, 100%, 40%);">+ while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT))</span><br><span style="color: hsl(120, 100%, 40%);">+ ;</span><br><span> }</span><br><span> </span><br><span> static unsigned char mtk_uart_rx_byte(void)</span><br><span>diff --git a/src/soc/mediatek/mt8173/wdt.c b/src/soc/mediatek/mt8173/wdt.c</span><br><span>index 22f1c87..85fdbf5 100644</span><br><span>--- a/src/soc/mediatek/mt8173/wdt.c</span><br><span>+++ b/src/soc/mediatek/mt8173/wdt.c</span><br><span>@@ -20,7 +20,7 @@</span><br><span> #include <soc/wdt.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct mt8173_wdt_regs * const mt8173_wdt = (void *)RGU_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8173_wdt_regs *const mt8173_wdt = (void *)RGU_BASE;</span><br><span> </span><br><span> int mtk_wdt_init(void)</span><br><span> {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26880">change 26880</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26880"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib36c99b141c94220776fab606eb36af8f64f65bb </div>
<div style="display:none"> Gerrit-Change-Number: 26880 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>