<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26881">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek: Refactor to sharing code among similar SOCs<br><br>This patch refactor cbmem and timer code which will be reused among<br>similar SOCs.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=the refactored code works fine on the new platform (with the rest<br> of the patches applied) and Elm platform<br><br>Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232<br>Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com><br>---<br>M src/soc/mediatek/mt8173/Makefile.inc<br>M src/soc/mediatek/mt8173/cbmem.c<br>A src/soc/mediatek/mt8173/common_timer.c<br>M src/soc/mediatek/mt8173/include/soc/timer.h<br>M src/soc/mediatek/mt8173/timer.c<br>5 files changed, 79 insertions(+), 72 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/26881/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>index fecd7f1..3aa463a 100644</span><br><span>--- a/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>+++ b/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>@@ -20,6 +20,7 @@</span><br><span> bootblock-y += i2c.c</span><br><span> bootblock-y += pll.c</span><br><span> bootblock-y += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += common_timer.c</span><br><span> bootblock-y += timer.c</span><br><span> </span><br><span> ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)</span><br><span>@@ -37,6 +38,7 @@</span><br><span> </span><br><span> verstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += common_timer.c</span><br><span> verstage-y += timer.c</span><br><span> verstage-y += wdt.c</span><br><span> verstage-$(CONFIG_SPI_FLASH) += flash_controller.c</span><br><span>@@ -46,6 +48,7 @@</span><br><span> </span><br><span> romstage-$(CONFIG_SPI_FLASH) += flash_controller.c</span><br><span> romstage-y += pll.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += common_timer.c</span><br><span> romstage-y += timer.c</span><br><span> </span><br><span> romstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span>@@ -64,6 +67,7 @@</span><br><span> ramstage-y += spi.c</span><br><span> ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c</span><br><span> ramstage-y += soc.c mtcmos.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += common_timer.c</span><br><span> ramstage-y += timer.c</span><br><span> ramstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span> ramstage-y += pmic_wrap.c mt6391.c i2c.c</span><br><span>diff --git a/src/soc/mediatek/mt8173/cbmem.c b/src/soc/mediatek/mt8173/cbmem.c</span><br><span>index 1967a2c..8906565 100644</span><br><span>--- a/src/soc/mediatek/mt8173/cbmem.c</span><br><span>+++ b/src/soc/mediatek/mt8173/cbmem.c</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2015 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -19,7 +19,9 @@</span><br><span> #include <symbols.h></span><br><span> #include <soc/emi.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void *cbmem_top(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return (void *)min((uintptr_t)_dram + sdram_size(), (uintptr_t)4 * GiB);</span><br><span style="color: hsl(120, 100%, 40%);">+ return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS);</span><br><span> }</span><br><span>diff --git a/src/soc/mediatek/mt8173/common_timer.c b/src/soc/mediatek/mt8173/common_timer.c</span><br><span>new file mode 100644</span><br><span>index 0000000..6e4315c</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8173/common_timer.c</span><br><span>@@ -0,0 +1,47 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <compiler.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <thread.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mtk_gpt_regs *const mtk_gpt = (void *)GPT_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void timer_prepare(void) { /* do nothing */ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void timer_monotonic_get(struct mono_time *mt)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ mono_time_set_usecs(mt, read32(&mtk_gpt->gpt4_cnt) / GPT4_MHZ);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void init_timer(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ timer_prepare();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable GPT4 and clear the counter */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&mtk_gpt->gpt4_con, GPT_CON_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_gpt->gpt4_con, GPT_CON_CLR);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set clock source to system clock and set clock divider to 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_gpt->gpt4_clk, GPT_SYS_CLK | GPT_CLK_DIV1);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set operation mode to FREERUN mode and enable GTP4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mtk_gpt->gpt4_con, GPT_CON_EN | GPT_MODE_FREERUN);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/timer.h b/src/soc/mediatek/mt8173/include/soc/timer.h</span><br><span>index 39aacb4..babcbba 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/timer.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/timer.h</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2015 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -13,59 +13,38 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __SOC_MEDIATEK_MT8173_TIMER_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __SOC_MEDIATEK_MT8173_TIMER_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_MEDIATEK_COMMON_TIMER_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_MEDIATEK_COMMON_TIMER_H</span><br><span> </span><br><span> #include <soc/addressmap.h></span><br><span> #include <types.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-struct mt8173_gpt_regs {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 irqen;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 irqsta;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 irqack;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt1_con;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt1_clk;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt1_cnt;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt1_compare;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt2_con;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt2_clk;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt2_cnt;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt2_compare;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt3_con;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt3_clk;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt3_cnt;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt3_compare;</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPT4_MHZ 13</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mtk_gpt_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved[16];</span><br><span> u32 gpt4_con;</span><br><span> u32 gpt4_clk;</span><br><span> u32 gpt4_cnt;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt4_compare;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt5_con;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt5_clk;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt5_cnt;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt5_compare;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt6_con;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt6_clk;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt6_cntl;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt6_comparel;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved1[2];</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt6_cnth;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpt6_compareh;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 apxgpt_irqmask;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 apxgpt_irqmask1;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct mt8173_gpt_regs *const mt8173_gpt = (void *)GPT_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_gpt_regs, gpt4_con, 0x0040);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_gpt_regs, gpt4_clk, 0x0044);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_gpt_regs, gpt4_cnt, 0x0048);</span><br><span> </span><br><span> enum {</span><br><span style="color: hsl(0, 100%, 40%);">- GPT_CON_EN = 0x01,</span><br><span style="color: hsl(0, 100%, 40%);">- GPT_CON_CLR = 0x02,</span><br><span style="color: hsl(0, 100%, 40%);">- GPT_MODE_ONE_SHOT = 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- GPT_MODE_REPEAT = 0x10,</span><br><span style="color: hsl(0, 100%, 40%);">- GPT_MODE_KEEP_GO = 0x20,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPT_CON_EN = 0x01,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPT_CON_CLR = 0x02,</span><br><span> GPT_MODE_FREERUN = 0x30,</span><br><span style="color: hsl(0, 100%, 40%);">- GPT_SYS_CLK = 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- GPT_SYS_RTC = 0x01,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPT_SYS_CLK = 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPT_CLK_DIV1 = 0x00,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* __SOC_MEDIATEK_MT8173_TIMER_H__ */</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This is defined as weak no-ops that can be overridden by legacy SOCs. Some</span><br><span style="color: hsl(120, 100%, 40%);">+ * legacy SOCs need specific settings before init timer. And we expect future</span><br><span style="color: hsl(120, 100%, 40%);">+ * SOCs will not need it.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void timer_prepare(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/mediatek/mt8173/timer.c b/src/soc/mediatek/mt8173/timer.c</span><br><span>index b8d8a64..300c65a 100644</span><br><span>--- a/src/soc/mediatek/mt8173/timer.c</span><br><span>+++ b/src/soc/mediatek/mt8173/timer.c</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2015 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -14,26 +14,10 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <timer.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <thread.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/addressmap.h></span><br><span> #include <soc/mcucfg.h></span><br><span> #include <soc/timer.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define GPT4_MHZ 13</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void timer_monotonic_get(struct mono_time *mt)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- mono_time_set_usecs(mt, read32(&mt8173_gpt->gpt4_cnt) / GPT4_MHZ);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * init_timer - initialize timer</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-void init_timer(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void timer_prepare(void)</span><br><span> {</span><br><span> /* Set XGPT_IDX to 0, then the bit field of XGPT_CTL will be programmed</span><br><span> * with following definition.</span><br><span>@@ -48,13 +32,4 @@</span><br><span> write32(&mt8173_mcucfg->xgpt_idx, 0);</span><br><span> /* Set clock mode to 13Mhz and enable XGPT */</span><br><span> write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / GPT4_MHZ) << 8)));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable GPT4 and clear the counter */</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&mt8173_gpt->gpt4_con, GPT_CON_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&mt8173_gpt->gpt4_con, GPT_CON_CLR);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set clock source to system clock and set clock divider to 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_gpt->gpt4_clk, GPT_SYS_CLK | 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set operation mode to FREERUN mode and enable GTP4 */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(&mt8173_gpt->gpt4_con, GPT_CON_EN | GPT_MODE_FREERUN);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26881">change 26881</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26881"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232 </div>
<div style="display:none"> Gerrit-Change-Number: 26881 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>