<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26854">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/octopus: Enable wake-over-wifi for octopus variants<br><br>This change enables wake-over-wifi functionality for all octopus<br>variants by making the following changeS:<br><br>1. Configure GPIO_119 as SCI active-low<br>2. Update GPE0_DW1 to include the group that GPIO_119 falls under<br>3. Add wake property to wifi device<br><br>BUG=b:77224247<br>TEST=Verified that wake-over-wifi works on yorp.<br><br>Change-Id: Ibae199c43e4d96da4c2f68f71a849c2f23d3e7b9<br>Signed-off-by: Furquan Shaikh <furquan@google.com><br>---<br>M src/mainboard/google/octopus/variants/baseboard/devicetree.cb<br>M src/mainboard/google/octopus/variants/baseboard/gpio.c<br>M src/mainboard/google/octopus/variants/bip/devicetree.cb<br>M src/mainboard/google/octopus/variants/bip/gpio.c<br>4 files changed, 6 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/26854/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>index 97bb691..1411a7c 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>@@ -29,7 +29,7 @@</span><br><span> # route, i.e., if this route changes then the affected GPE</span><br><span> # offset bits also need to be changed. This sets the PMC register</span><br><span> # GPE_CFG fields.</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw1" = "PMC_GPE_NW_63_32"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "PMC_GPE_N_63_32"</span><br><span> register "gpe0_dw2" = "PMC_GPE_N_95_64"</span><br><span> register "gpe0_dw3" = "PMC_GPE_NW_31_0"</span><br><span> </span><br><span>@@ -117,6 +117,7 @@</span><br><span> device pci 12.0 off end # - SATA</span><br><span> device pci 13.0 on</span><br><span> chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW1_11"</span><br><span> device pci 00.0 on end</span><br><span> end</span><br><span> end # - PCIe-A 0 Onboard M2 Slot(Wifi)</span><br><span>diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c</span><br><span>index f839850..c7d8d3d 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c</span><br><span>@@ -166,8 +166,7 @@</span><br><span> PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */</span><br><span> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE1_B */</span><br><span> PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_WAKE2_B -- unused */</span><br><span style="color: hsl(0, 100%, 40%);">- //TODO Reef uses PCIE_WAKE0 as GPI_SCI. Whats the difference?</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_119, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE3_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */</span><br><span> </span><br><span> /* PCIE_CLKREQ[0:3]_B */</span><br><span> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/</span><br><span>diff --git a/src/mainboard/google/octopus/variants/bip/devicetree.cb b/src/mainboard/google/octopus/variants/bip/devicetree.cb</span><br><span>index 7520110..277cb76 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/bip/devicetree.cb</span><br><span>+++ b/src/mainboard/google/octopus/variants/bip/devicetree.cb</span><br><span>@@ -29,7 +29,7 @@</span><br><span> # route, i.e., if this route changes then the affected GPE</span><br><span> # offset bits also need to be changed. This sets the PMC register</span><br><span> # GPE_CFG fields.</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw1" = "PMC_GPE_NW_63_32"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "PMC_GPE_N_63_32"</span><br><span> register "gpe0_dw2" = "PMC_GPE_N_95_64"</span><br><span> register "gpe0_dw3" = "PMC_GPE_NW_31_0"</span><br><span> </span><br><span>@@ -117,6 +117,7 @@</span><br><span> device pci 12.0 off end # - SATA</span><br><span> device pci 13.0 on</span><br><span> chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW1_11"</span><br><span> device pci 00.0 on end</span><br><span> end</span><br><span> end # - PCIe-A 0 Onboard M2 Slot(Wifi)</span><br><span>diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c</span><br><span>index e809ca2..d7396ca 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/bip/gpio.c</span><br><span>+++ b/src/mainboard/google/octopus/variants/bip/gpio.c</span><br><span>@@ -164,8 +164,7 @@</span><br><span> PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */</span><br><span> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE1_B */</span><br><span> PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_WAKE2_B -- unused */</span><br><span style="color: hsl(0, 100%, 40%);">- //TODO Reef uses PCIE_WAKE0 as GPI_SCI. Whats the difference?</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_119, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE3_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */</span><br><span> </span><br><span> /* PCIE_CLKREQ[0:3]_B */</span><br><span> PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26854">change 26854</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26854"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibae199c43e4d96da4c2f68f71a849c2f23d3e7b9 </div>
<div style="display:none"> Gerrit-Change-Number: 26854 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>