<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/26636">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/siemens: Get rid of whitespace before tab<br><br>Change-Id: Ic334f65e5c27d4f773f81fc1c9e3df7d63d47a11<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>Reviewed-on: https://review.coreboot.org/26636<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Patrick Georgi <pgeorgi@google.com><br>---<br>M src/mainboard/siemens/mc_tcu3/devicetree.cb<br>M src/mainboard/siemens/mc_tcu3/gpio.c<br>M src/mainboard/siemens/mc_tcu3/irqroute.h<br>3 files changed, 10 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_tcu3/devicetree.cb b/src/mainboard/siemens/mc_tcu3/devicetree.cb</span><br><span>index 2a8183d..433eebe 100644</span><br><span>--- a/src/mainboard/siemens/mc_tcu3/devicetree.cb</span><br><span>+++ b/src/mainboard/siemens/mc_tcu3/devicetree.cb</span><br><span>@@ -59,7 +59,7 @@</span><br><span> device pci 18.7 on end # 8086 0F47 - I2C Port 7</span><br><span> device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine</span><br><span> device pci 1b.0 on end # 8086 0F04 - HD Audio</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.0 on # 8086 0F48 - PCIe Root Port 1 (x4 slot)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on # 8086 0F48 - PCIe Root Port 1 (x4 slot)</span><br><span> device pci 0.0 on end # 8086 1538 - Intel i210 MACPHY</span><br><span> end</span><br><span> device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot)</span><br><span>diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c</span><br><span>index c803998..23c6f96 100644</span><br><span>--- a/src/mainboard/siemens/mc_tcu3/gpio.c</span><br><span>+++ b/src/mainboard/siemens/mc_tcu3/gpio.c</span><br><span>@@ -160,14 +160,14 @@</span><br><span> /* SSUS GPIOs (GPIO_S5) */</span><br><span> static const struct soc_gpio_map gpssus_gpio_map[] = {</span><br><span> GPIO_INPUT_PD_10K, /* GPIO_S5[00] RESERVED */</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_INPUT_PD_10K, /* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_INPUT_PD_10K, /* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */</span><br><span> GPIO_INPUT_PD_10K, /* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */</span><br><span> GPIO_INPUT_PD_10K, /* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */</span><br><span> GPIO_INPUT_PD_10K, /* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */</span><br><span> GPIO_INPUT_PD_10K, /* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */</span><br><span> GPIO_INPUT_PD_10K, /* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */</span><br><span> GPIO_INPUT_PD_10K, /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_INPUT_PU_10K, /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_INPUT_PU_10K, /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */</span><br><span> GPIO_INPUT_PU_10K, /* GPIO_S5[09] RESERVED RESERVED ESERVED RESERVED */</span><br><span> GPIO_OUT_HIGH, /* GPIO_S5[10] RESERVED RESERVED RESERVED */</span><br><span> GPIO_DEFAULT, /* PMC_SUSPWRDNACK GPIO_S5[11] - - */</span><br><span>diff --git a/src/mainboard/siemens/mc_tcu3/irqroute.h b/src/mainboard/siemens/mc_tcu3/irqroute.h</span><br><span>index a24be3e..41b990b 100644</span><br><span>--- a/src/mainboard/siemens/mc_tcu3/irqroute.h</span><br><span>+++ b/src/mainboard/siemens/mc_tcu3/irqroute.h</span><br><span>@@ -20,14 +20,14 @@</span><br><span> #include <soc/intel/fsp_baytrail/include/soc/pci_devs.h></span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- *IR02h GFX INT(A) - PIRQ A</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR02h GFX INT(A) - PIRQ A</span><br><span> *IR10h EMMC INT(ABCD) - PIRQ DEFG</span><br><span style="color: hsl(0, 100%, 40%);">- *IR11h SDIO INT(A) - PIRQ B</span><br><span style="color: hsl(0, 100%, 40%);">- *IR12h SD INT(A) - PIRQ C</span><br><span style="color: hsl(0, 100%, 40%);">- *IR13h SATA INT(A) - PIRQ D</span><br><span style="color: hsl(0, 100%, 40%);">- *IR14h XHCI INT(A) - PIRQ E</span><br><span style="color: hsl(0, 100%, 40%);">- *IR15h LP Audio INT(A) - PIRQ F</span><br><span style="color: hsl(0, 100%, 40%);">- *IR17h MMC INT(A) - PIRQ F</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR11h SDIO INT(A) - PIRQ B</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR12h SD INT(A) - PIRQ C</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR13h SATA INT(A) - PIRQ D</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR14h XHCI INT(A) - PIRQ E</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR15h LP Audio INT(A) - PIRQ F</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR17h MMC INT(A) - PIRQ F</span><br><span> *IR18h SIO INT(ABCD) - PIRQ BADC</span><br><span> *IR1Ah TXE INT(A) - PIRQ F</span><br><span> *IR1Bh HD Audio INT(A) - PIRQ G</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26636">change 26636</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: Ic334f65e5c27d4f773f81fc1c9e3df7d63d47a11 </div>
<div style="display:none"> Gerrit-Change-Number: 26636 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>