<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26819">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Make use of SkipMpInit for MP Init<br><br>This patch provides option for mainboard to skip coreboot MP<br>initialization if required based on use_fsp_mp_init.<br><br>Option for mainboard to skip coreboot MP initialization<br>* 0 = Make use of coreboot MP Init<br>* 1 = Make use of FSP MP Init<br><br>Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb<br>M src/mainboard/google/zoombini/variants/meowth/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>M src/soc/intel/cannonlake/chip.c<br>M src/soc/intel/cannonlake/chip.h<br>6 files changed, 7 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/26819/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>index 512354e..6f70dfb 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>@@ -20,7 +20,6 @@</span><br><span> </span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">- register "FspSkipMpInit" = "1"</span><br><span> register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcEnabled" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>index 4076ea6..7d89b78 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>@@ -29,7 +29,6 @@</span><br><span> </span><br><span> # FSP configuration</span><br><span> register "SaGv" = "SaGv_Enabled"</span><br><span style="color: hsl(0, 100%, 40%);">- register "FspSkipMpInit" = "1"</span><br><span> register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcEnabled" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>index 18aa65d..d5d806c 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>@@ -6,7 +6,6 @@</span><br><span> </span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">- register "FspSkipMpInit" = "1"</span><br><span> register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcEnabled" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>index 8bcb850..4c62800 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>@@ -6,7 +6,6 @@</span><br><span> </span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">- register "FspSkipMpInit" = "1"</span><br><span> register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcEnabled" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index 0c4232c..924764a 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -295,7 +295,7 @@</span><br><span> </span><br><span> params->Heci3Enabled = config->Heci3Enabled;</span><br><span> params->Device4Enable = config->Device4Enable;</span><br><span style="color: hsl(0, 100%, 40%);">- params->SkipMpInit = config->FspSkipMpInit;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SkipMpInit = !config->use_fsp_mp_init;</span><br><span> </span><br><span> /* VrConfig Settings for 5 domains</span><br><span> * 0 = System Agent, 1 = IA Core, 2 = Ring,</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h</span><br><span>index 8fdb964..d943f9c 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.h</span><br><span>+++ b/src/soc/intel/cannonlake/chip.h</span><br><span>@@ -206,7 +206,12 @@</span><br><span> CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */</span><br><span> } chipset_lockdown;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t FspSkipMpInit;</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Option for mainboard to skip coreboot MP initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Make use of coreboot MP Init</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Make use of FSP MP Init</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t use_fsp_mp_init;</span><br><span> /* VrConfig Settings for 5 domains</span><br><span> * 0 = System Agent, 1 = IA Core, 2 = Ring,</span><br><span> * 3 = GT unsliced, 4 = GT sliced */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26819">change 26819</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26819"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2 </div>
<div style="display:none"> Gerrit-Change-Number: 26819 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>