<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/26649">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/drivers: Get rid of whitespace before tab<br><br>Change-Id: Ia9ca055679c0332613afb2bb2ed86df165de3baf<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>Reviewed-on: https://review.coreboot.org/26649<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Patrick Georgi <pgeorgi@google.com><br>---<br>M src/drivers/amd/agesa/acpi_tables.c<br>M src/drivers/aspeed/common/ast_tables.h<br>M src/drivers/generic/gpio_keys/gpio_keys.c<br>M src/drivers/intel/fsp1_0/fsp_util.c<br>M src/drivers/intel/fsp1_1/cache_as_ram.inc<br>M src/drivers/intel/gma/acpi.c<br>M src/drivers/net/ne2k.c<br>M src/drivers/xgi/common/initdef.h<br>M src/drivers/xgi/common/vstruct.h<br>9 files changed, 86 insertions(+), 86 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/drivers/amd/agesa/acpi_tables.c b/src/drivers/amd/agesa/acpi_tables.c</span><br><span>index 5335c02..2f0cde8 100644</span><br><span>--- a/src/drivers/amd/agesa/acpi_tables.c</span><br><span>+++ b/src/drivers/amd/agesa/acpi_tables.c</span><br><span>@@ -26,11 +26,11 @@</span><br><span> IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) || \</span><br><span> IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00730F01)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define HAS_ACPI_SRAT TRUE</span><br><span style="color: hsl(0, 100%, 40%);">-#define HAS_ACPI_SLIT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define HAS_ACPI_SRAT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define HAS_ACPI_SLIT TRUE</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">-#define HAS_ACPI_SRAT FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#define HAS_ACPI_SLIT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define HAS_ACPI_SRAT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define HAS_ACPI_SLIT FALSE</span><br><span> #endif</span><br><span> </span><br><span> /* We will reference AmdLateParams later to copy ACPI tables. */</span><br><span>diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h</span><br><span>index 3608d5a..6c20f36 100644</span><br><span>--- a/src/drivers/aspeed/common/ast_tables.h</span><br><span>+++ b/src/drivers/aspeed/common/ast_tables.h</span><br><span>@@ -49,63 +49,63 @@</span><br><span> #define SyncNN (NVSync | NHSync)</span><br><span> </span><br><span> /* DCLK Index */</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK25_175 0x00</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK28_322 0x01</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK31_5 0x02</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK36 0x03</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK40 0x04</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK49_5 0x05</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK50 0x06</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK56_25 0x07</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK65 0x08</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK75 0x09</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK78_75 0x0A</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK94_5 0x0B</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK108 0x0C</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK135 0x0D</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK157_5 0x0E</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK162 0x0F</span><br><span style="color: hsl(0, 100%, 40%);">-/* #define VCLK193_25 0x10 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK154 0x10</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK83_5 0x11</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK106_5 0x12</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK146_25 0x13</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK148_5 0x14</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK71 0x15</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK88_75 0x16</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK119 0x17</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK85_5 0x18</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK97_75 0x19</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCLK118_25 0x1A</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK25_175 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK28_322 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK31_5 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK36 0x03</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK40 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK49_5 0x05</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK50 0x06</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK56_25 0x07</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK65 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK75 0x09</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK78_75 0x0A</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK94_5 0x0B</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK108 0x0C</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK135 0x0D</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK157_5 0x0E</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK162 0x0F</span><br><span style="color: hsl(120, 100%, 40%);">+/* #define VCLK193_25 0x10 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK154 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK83_5 0x11</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK106_5 0x12</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK146_25 0x13</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK148_5 0x14</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK71 0x15</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK88_75 0x16</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK119 0x17</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK85_5 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK97_75 0x19</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCLK118_25 0x1A</span><br><span> </span><br><span> static struct ast_vbios_dclk_info dclk_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x76, 0x63, 0x01}, /* 03: VCLK36 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0xEE, 0x67, 0x01}, /* 04: VCLK40 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0xC6, 0x64, 0x01}, /* 06: VCLK50 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x80, 0x64, 0x00}, /* 08: VCLK65 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x7B, 0x63, 0x00}, /* 09: VCLK75 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x85, 0x24, 0x00}, /* 0D: VCLK135 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x47, 0x6c, 0x80}, /* 15: VCLK71 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x77, 0x58, 0x80}, /* 17: VCLK119 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x76, 0x63, 0x01}, /* 03: VCLK36 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0xEE, 0x67, 0x01}, /* 04: VCLK40 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0xC6, 0x64, 0x01}, /* 06: VCLK50 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x80, 0x64, 0x00}, /* 08: VCLK65 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x7B, 0x63, 0x00}, /* 09: VCLK75 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x85, 0x24, 0x00}, /* 0D: VCLK135 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x47, 0x6c, 0x80}, /* 15: VCLK71 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x77, 0x58, 0x80}, /* 17: VCLK119 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */</span><br><span> };</span><br><span> </span><br><span> static struct ast_vbios_stdtable vbios_stdtable[] = {</span><br><span>@@ -188,14 +188,14 @@</span><br><span> (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E },</span><br><span> { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */</span><br><span> (SyncNN | Charx8Dot) , 75, 3, 0x2E },</span><br><span style="color: hsl(0, 100%, 40%);">- { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */</span><br><span> (SyncNN | Charx8Dot) , 85, 4, 0x2E },</span><br><span style="color: hsl(0, 100%, 40%);">- { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */</span><br><span> (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E },</span><br><span> };</span><br><span> </span><br><span> static struct ast_vbios_enhtable res_800x600[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */</span><br><span style="color: hsl(120, 100%, 40%);">+ {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */</span><br><span> (SyncPP | Charx8Dot), 56, 1, 0x30 },</span><br><span> {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */</span><br><span> (SyncPP | Charx8Dot), 60, 2, 0x30 },</span><br><span>@@ -268,7 +268,7 @@</span><br><span> </span><br><span> /* 16:10 */</span><br><span> static struct ast_vbios_enhtable res_1280x800[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */</span><br><span style="color: hsl(120, 100%, 40%);">+ {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */</span><br><span> (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 },</span><br><span> {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */</span><br><span> (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 },</span><br><span>@@ -287,7 +287,7 @@</span><br><span> };</span><br><span> </span><br><span> static struct ast_vbios_enhtable res_1680x1050[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */</span><br><span style="color: hsl(120, 100%, 40%);">+ {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */</span><br><span> (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 },</span><br><span> {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */</span><br><span> (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 },</span><br><span>@@ -296,7 +296,7 @@</span><br><span> };</span><br><span> </span><br><span> static struct ast_vbios_enhtable res_1920x1200[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB*/</span><br><span style="color: hsl(120, 100%, 40%);">+ {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB*/</span><br><span> (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 },</span><br><span> {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB */</span><br><span> (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 },</span><br><span>diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c</span><br><span>index cbaf8cf..6120981 100644</span><br><span>--- a/src/drivers/generic/gpio_keys/gpio_keys.c</span><br><span>+++ b/src/drivers/generic/gpio_keys/gpio_keys.c</span><br><span>@@ -85,7 +85,7 @@</span><br><span> acpi_dp_add_string(dsd, "compatible", drv_string);</span><br><span> if (config->is_polled)</span><br><span> acpi_dp_add_integer(dsd, "poll-interval",</span><br><span style="color: hsl(0, 100%, 40%);">- config->poll_interval);</span><br><span style="color: hsl(120, 100%, 40%);">+ config->poll_interval);</span><br><span> /* Child device defining key */</span><br><span> child = gpio_keys_add_child_node(config, path);</span><br><span> if (child)</span><br><span>@@ -112,8 +112,8 @@</span><br><span> </span><br><span> static struct device_operations gpio_keys_ops = {</span><br><span> .read_resources = DEVICE_NOOP,</span><br><span style="color: hsl(0, 100%, 40%);">- .set_resources = DEVICE_NOOP,</span><br><span style="color: hsl(0, 100%, 40%);">- .enable_resources = DEVICE_NOOP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .set_resources = DEVICE_NOOP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_resources = DEVICE_NOOP,</span><br><span> .acpi_name = &gpio_keys_acpi_name,</span><br><span> .acpi_fill_ssdt_generator = &gpio_keys_fill_ssdt_generator,</span><br><span> };</span><br><span>diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c</span><br><span>index 17b2fd4..5a6321d 100644</span><br><span>--- a/src/drivers/intel/fsp1_0/fsp_util.c</span><br><span>+++ b/src/drivers/intel/fsp1_0/fsp_util.c</span><br><span>@@ -113,7 +113,7 @@</span><br><span> );</span><br><span> #else</span><br><span> volatile u8 *fsp_ptr;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* __PRE_RAM__ */</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __PRE_RAM__ */</span><br><span> </span><br><span> /* The FSP is stored in CBFS */</span><br><span> fsp_ptr = (u8 *) CONFIG_FSP_LOC;</span><br><span>diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc</span><br><span>index fc66208..af6f3a9 100644</span><br><span>--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc</span><br><span>+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc</span><br><span>@@ -131,7 +131,7 @@</span><br><span> movd %mm1, %eax</span><br><span> pushl %eax /* tsc[63:32] */</span><br><span> movd %mm0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- pushl %eax /* tsc[31:0] */</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %eax /* tsc[31:0] */</span><br><span> pushl %esp /* pointer to cache_as_ram_params */</span><br><span> </span><br><span> /* Save FSP_INFO_HEADER location in ebx */</span><br><span>diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c</span><br><span>index f62e8ee..65117aa 100644</span><br><span>--- a/src/drivers/intel/gma/acpi.c</span><br><span>+++ b/src/drivers/intel/gma/acpi.c</span><br><span>@@ -72,7 +72,7 @@</span><br><span> /*</span><br><span> Method (_BCL, 0, NotSerialized)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (^^XBCL())</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (^^XBCL())</span><br><span> }</span><br><span> */</span><br><span> acpigen_write_method("_BCL", 0);</span><br><span>@@ -83,7 +83,7 @@</span><br><span> /*</span><br><span> Method (_BCM, 1, NotSerialized)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- ^^XBCM(Arg0)</span><br><span style="color: hsl(120, 100%, 40%);">+ ^^XBCM(Arg0)</span><br><span> }</span><br><span> */</span><br><span> acpigen_write_method("_BCM", 1);</span><br><span>@@ -94,7 +94,7 @@</span><br><span> /*</span><br><span> Method (_BQC, 0, NotSerialized)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (^^XBQC())</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (^^XBQC())</span><br><span> }</span><br><span> */</span><br><span> acpigen_write_method("_BQC", 0);</span><br><span>diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c</span><br><span>index bec1d78..9614296 100644</span><br><span>--- a/src/drivers/net/ne2k.c</span><br><span>+++ b/src/drivers/net/ne2k.c</span><br><span>@@ -437,7 +437,7 @@</span><br><span> res->gran = 5;</span><br><span> res->limit = res->base + res->size - 1;</span><br><span> res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_STORED |</span><br><span style="color: hsl(0, 100%, 40%);">- IORESOURCE_ASSIGNED;</span><br><span style="color: hsl(120, 100%, 40%);">+ IORESOURCE_ASSIGNED;</span><br><span> return;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/drivers/xgi/common/initdef.h b/src/drivers/xgi/common/initdef.h</span><br><span>index 0195757..e164e6b 100644</span><br><span>--- a/src/drivers/xgi/common/initdef.h</span><br><span>+++ b/src/drivers/xgi/common/initdef.h</span><br><span>@@ -42,7 +42,7 @@</span><br><span> * * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF</span><br><span> * * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Author: Thomas Winischhofer <thomas@winischhofer.net></span><br><span style="color: hsl(120, 100%, 40%);">+ * Author: Thomas Winischhofer <thomas@winischhofer.net></span><br><span> *</span><br><span> */</span><br><span> </span><br><span>@@ -80,7 +80,7 @@</span><br><span> #define VB_SIS307T 0x0080</span><br><span> #define VB_SIS307LV 0x0100</span><br><span> #define VB_UMC 0x4000</span><br><span style="color: hsl(0, 100%, 40%);">-#define VB_NoLCD 0x8000</span><br><span style="color: hsl(120, 100%, 40%);">+#define VB_NoLCD 0x8000</span><br><span> #define VB_SIS30xB (VB_SIS301B | VB_SIS301C | VB_SIS302B | VB_SIS307T)</span><br><span> #define VB_SIS30xC (VB_SIS301C | VB_SIS307T)</span><br><span> #define VB_SISTMDS (VB_SIS301 | VB_SIS301B | VB_SIS301C | VB_SIS302B | VB_SIS307T)</span><br><span>@@ -110,10 +110,10 @@</span><br><span> #define SetCRT2ToSCART 0x0010</span><br><span> #define SetCRT2ToLCD 0x0020</span><br><span> #define SetCRT2ToRAMDAC 0x0040</span><br><span style="color: hsl(0, 100%, 40%);">-#define SetCRT2ToHiVision 0x0080 /* for SiS bridge */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SetCRT2ToCHYPbPr SetCRT2ToHiVision /* for Chrontel */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SetCRT2ToHiVision 0x0080 /* for SiS bridge */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SetCRT2ToCHYPbPr SetCRT2ToHiVision /* for Chrontel */</span><br><span> #define SetNTSCTV 0x0000 /* CR 31 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SetPALTV 0x0100 /* Deprecated here, now in TVMode */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SetPALTV 0x0100 /* Deprecated here, now in TVMode */</span><br><span> #define SetInSlaveMode 0x0200</span><br><span> #define SetNotSimuMode 0x0400</span><br><span> #define SetNotSimuTVMode SetNotSimuMode</span><br><span>@@ -128,7 +128,7 @@</span><br><span> /* v-- Needs change in sis_vga.c if changed (GPIO) --v */</span><br><span> #define SetCRT2ToTV (SetCRT2ToYPbPr525750|SetCRT2ToHiVision|SetCRT2ToSCART|SetCRT2ToSVIDEO|SetCRT2ToAVIDEO)</span><br><span> #define SetCRT2ToTVNoYPbPrHiVision (SetCRT2ToSCART | SetCRT2ToSVIDEO | SetCRT2ToAVIDEO)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SetCRT2ToTVNoHiVision (SetCRT2ToYPbPr525750 | SetCRT2ToSCART | SetCRT2ToSVIDEO | SetCRT2ToAVIDEO)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SetCRT2ToTVNoHiVision (SetCRT2ToYPbPr525750 | SetCRT2ToSCART | SetCRT2ToSVIDEO | SetCRT2ToAVIDEO)</span><br><span> </span><br><span> /* SiS_ModeType */</span><br><span> #define ModeText 0x00</span><br><span>@@ -159,7 +159,7 @@</span><br><span> /* Infoflag */</span><br><span> #define SupportTV 0x0008</span><br><span> #define SupportTV1024 0x0800</span><br><span style="color: hsl(0, 100%, 40%);">-#define SupportCHTV 0x0800</span><br><span style="color: hsl(120, 100%, 40%);">+#define SupportCHTV 0x0800</span><br><span> #define Support64048060Hz 0x0800 /* Special for 640x480 LCD */</span><br><span> #define SupportHiVision 0x0010</span><br><span> #define SupportYPbPr750p 0x1000</span><br><span>@@ -297,7 +297,7 @@</span><br><span> #define LCDSyncShift 6</span><br><span> </span><br><span> /* CR38 (315 series) */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EnableDualEdge 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define EnableDualEdge 0x01</span><br><span> #define SetToLCDA 0x02 /* LCD channel A (301C/302B/30x(E)LV and 650+LVDS only) */</span><br><span> #define EnableCHScart 0x04 /* Scart on Ch7019 (unofficial definition - TW) */</span><br><span> #define EnableCHYPbPr 0x08 /* YPbPr on Ch7019 (480i HDTV); only on 650/Ch7019 systems */</span><br><span>@@ -605,7 +605,7 @@</span><br><span> #define _PanelType0E 0x70</span><br><span> #define _PanelType0F 0x78</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define PRIMARY_VGA 0 /* 1: SiS is primary vga 0:SiS is secondary vga */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRIMARY_VGA 0 /* 1: SiS is primary vga 0:SiS is secondary vga */</span><br><span> </span><br><span> #define BIOSIDCodeAddr 0x235 /* Offsets to ptrs in BIOS image */</span><br><span> #define OEMUtilIDCodeAddr 0x237</span><br><span>@@ -650,7 +650,7 @@</span><br><span> </span><br><span> /*</span><br><span> =============================================================</span><br><span style="color: hsl(0, 100%, 40%);">- for 315 series (old data layout)</span><br><span style="color: hsl(120, 100%, 40%);">+ for 315 series (old data layout)</span><br><span> =============================================================</span><br><span> */</span><br><span> #define SoftDRAMType 0x80</span><br><span>diff --git a/src/drivers/xgi/common/vstruct.h b/src/drivers/xgi/common/vstruct.h</span><br><span>index d14a182..3e530a2 100644</span><br><span>--- a/src/drivers/xgi/common/vstruct.h</span><br><span>+++ b/src/drivers/xgi/common/vstruct.h</span><br><span>@@ -42,7 +42,7 @@</span><br><span> * * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF</span><br><span> * * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Author: Thomas Winischhofer <thomas@winischhofer.net></span><br><span style="color: hsl(120, 100%, 40%);">+ * Author: Thomas Winischhofer <thomas@winischhofer.net></span><br><span> *</span><br><span> */</span><br><span> </span><br><span>@@ -230,7 +230,7 @@</span><br><span> unsigned char ChipType;</span><br><span> unsigned char ChipRevision;</span><br><span> void *ivideo;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char *VirtualRomBase;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned char *VirtualRomBase;</span><br><span> bool UseROM;</span><br><span> unsigned char SISIOMEMTYPE *VideoMemoryAddress;</span><br><span> unsigned int VideoMemorySize;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26649">change 26649</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26649"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: Ia9ca055679c0332613afb2bb2ed86df165de3baf </div>
<div style="display:none"> Gerrit-Change-Number: 26649 </div>
<div style="display:none"> Gerrit-PatchSet: 4 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>