<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26835">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/haswell: Use the common intel romstage_main function<br><br>Untested.<br><br>Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/haswell/Makefile.inc<br>M src/cpu/intel/haswell/haswell.h<br>M src/cpu/intel/haswell/romstage.c<br>M src/mainboard/google/beltino/romstage.c<br>M src/mainboard/google/slippy/romstage.c<br>M src/mainboard/intel/baskingridge/romstage.c<br>6 files changed, 6 insertions(+), 48 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/26835/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc</span><br><span>index a0c892a..bbd98da 100644</span><br><span>--- a/src/cpu/intel/haswell/Makefile.inc</span><br><span>+++ b/src/cpu/intel/haswell/Makefile.inc</span><br><span>@@ -2,6 +2,7 @@</span><br><span> ramstage-y += tsc_freq.c</span><br><span> romstage-y += romstage.c</span><br><span> romstage-y += tsc_freq.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += ../car/romstage.c</span><br><span> </span><br><span> ramstage-y += acpi.c</span><br><span> ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c</span><br><span>diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h</span><br><span>index 23efe6c..a951920 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell.h</span><br><span>+++ b/src/cpu/intel/haswell/haswell.h</span><br><span>@@ -163,24 +163,6 @@</span><br><span> unsigned long bist;</span><br><span> void (*copy_spd)(struct pei_data *);</span><br><span> };</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_romstage_entry(unsigned long bist);</span><br><span style="color: hsl(0, 100%, 40%);">-void romstage_common(const struct romstage_params *params);</span><br><span style="color: hsl(0, 100%, 40%);">-/* romstage_main is called from the cache-as-ram assembly file. The return</span><br><span style="color: hsl(0, 100%, 40%);">- * value is the stack value to be used for romstage once cache-as-ram is</span><br><span style="color: hsl(0, 100%, 40%);">- * torn down. The following values are pushed onto the stack to setup the</span><br><span style="color: hsl(0, 100%, 40%);">- * MTRRs:</span><br><span style="color: hsl(0, 100%, 40%);">- * +0: Number of MTRRs</span><br><span style="color: hsl(0, 100%, 40%);">- * +4: MTRR base 0 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +8: MTRR base 0 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * +12: MTRR mask 0 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +16: MTRR mask 0 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * +20: MTRR base 1 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +24: MTRR base 1 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * +28: MTRR mask 1 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +32: MTRR mask 1 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * ...</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void *romstage_main(unsigned long bist);</span><br><span> #endif</span><br><span> </span><br><span> #ifdef __SMM__</span><br><span>diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c</span><br><span>index 99ca557..e15290a 100644</span><br><span>--- a/src/cpu/intel/haswell/romstage.c</span><br><span>+++ b/src/cpu/intel/haswell/romstage.c</span><br><span>@@ -43,6 +43,7 @@</span><br><span> #include "southbridge/intel/lynxpoint/pch.h"</span><br><span> #include "southbridge/intel/lynxpoint/me.h"</span><br><span> #include <security/tpm/tis.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/romstage.h></span><br><span> </span><br><span> static inline void reset_system(void)</span><br><span> {</span><br><span>@@ -55,7 +56,7 @@</span><br><span> /* platform_enter_postcar() determines the stack to use after</span><br><span> * cache-as-ram is torn down as well as the MTRR settings to use,</span><br><span> * and continues execution in postcar stage. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void platform_enter_postcar(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void platform_enter_postcar(void)</span><br><span> {</span><br><span> struct postcar_frame pcf;</span><br><span> uintptr_t top_of_ram;</span><br><span>@@ -80,34 +81,6 @@</span><br><span> run_postcar_phase(&pcf);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void *romstage_main(unsigned long bist)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- const int num_guards = 4;</span><br><span style="color: hsl(0, 100%, 40%);">- const u32 stack_guard = 0xdeadbeef;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +</span><br><span style="color: hsl(0, 100%, 40%);">- CONFIG_DCACHE_RAM_SIZE -</span><br><span style="color: hsl(0, 100%, 40%);">- CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Setting up stack guards.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < num_guards; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- stack_base[i] = stack_guard;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_romstage_entry(bist);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check the stack. */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < num_guards; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (stack_base[i] == stack_guard)</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- platform_enter_postcar();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* We do not return here */</span><br><span style="color: hsl(0, 100%, 40%);">- return NULL;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void romstage_common(const struct romstage_params *params)</span><br><span> {</span><br><span> int boot_mode;</span><br><span>diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c</span><br><span>index b0468f5..cb719c3 100644</span><br><span>--- a/src/mainboard/google/beltino/romstage.c</span><br><span>+++ b/src/mainboard/google/beltino/romstage.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <stdlib.h></span><br><span> #include <string.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/romstage.h></span><br><span> #include <cpu/intel/haswell/haswell.h></span><br><span> #include <northbridge/intel/haswell/haswell.h></span><br><span> #include <northbridge/intel/haswell/raminit.h></span><br><span>diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c</span><br><span>index 82931fc..ec5d5ea 100644</span><br><span>--- a/src/mainboard/google/slippy/romstage.c</span><br><span>+++ b/src/mainboard/google/slippy/romstage.c</span><br><span>@@ -14,7 +14,7 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/haswell/haswell.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/romstage.h></span><br><span> #include "variant.h"</span><br><span> </span><br><span> </span><br><span>diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c</span><br><span>index 11e7444..5f51915 100644</span><br><span>--- a/src/mainboard/intel/baskingridge/romstage.c</span><br><span>+++ b/src/mainboard/intel/baskingridge/romstage.c</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #include <stdint.h></span><br><span> #include <stddef.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/romstage.h></span><br><span> #include <cpu/intel/haswell/haswell.h></span><br><span> #include <northbridge/intel/haswell/haswell.h></span><br><span> #include <northbridge/intel/haswell/raminit.h></span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26835">change 26835</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f </div>
<div style="display:none"> Gerrit-Change-Number: 26835 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>