<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26788">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/gm45: Switch to POSTCAR_STAGE<br><br>Change-Id: I02165cf63710bedcafe9287cbe8a1d1fe41ebae2<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>D src/cpu/intel/model_6ex/cache_as_ram.inc<br>M src/cpu/intel/socket_BGA956/Makefile.inc<br>M src/cpu/intel/socket_mPGA478MN/Makefile.inc<br>M src/northbridge/intel/gm45/Kconfig<br>M src/northbridge/intel/gm45/Makefile.inc<br>M src/northbridge/intel/gm45/ram_calc.c<br>6 files changed, 11 insertions(+), 282 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/26788/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span>deleted file mode 100644</span><br><span>index 4b85c07..0000000</span><br><span>--- a/src/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,267 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/post_code.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the BIST result. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-cache_as_ram:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x20)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Send INIT IPI to all excluding ourself. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x000C4500, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0xFEE00300, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, (%esi)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Zero out all fixed range and variable range MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $mtrr_table, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl $((mtrr_table_end - mtrr_table) >> 1), %edi</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %eax, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">-clear_mtrrs:</span><br><span style="color: hsl(0, 100%, 40%);">- movw (%esi), %bx</span><br><span style="color: hsl(0, 100%, 40%);">- movzx %bx, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- add $2, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- dec %edi</span><br><span style="color: hsl(0, 100%, 40%);">- jnz clear_mtrrs</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x22)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Configure the default memory type to uncacheable. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~0x00000cff), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x23)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Cache-as-RAM base address. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(MTRR_PHYS_BASE(0)), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x24)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Cache-as-RAM mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(MTRR_PHYS_MASK(0)), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_PHYSMASK_HI, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x25)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_DEF_TYPE_EN, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable L2 cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x11e, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $(1 << 8), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache (CR0.CD = 0, CR0.NW = 0). */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear the cache memory region. This will also fill up the cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CACHE_AS_RAM_BASE, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl %esi, %edi</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CACHE_AS_RAM_SIZE >> 2), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- // movl $0x23322332, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %eax, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- rep stosl</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x26)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable Cache-as-RAM mode by disabling cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache for our code in Flash because we do XIP here */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(1), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * IMPORTANT: The following calculation _must_ be done at runtime. See</span><br><span style="color: hsl(0, 100%, 40%);">- * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $copy_and_run, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_TYPE_WRPROT, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_MASK(1), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_PHYSMASK_HI, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x28)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup the stack. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Restore the BIST result. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %ebp, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %esp, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">- pushl %eax</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-before_romstage:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x29)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Call romstage.c main function. */</span><br><span style="color: hsl(0, 100%, 40%);">- call romstage_main</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save return value from romstage_main. It contains the stack to use</span><br><span style="color: hsl(0, 100%, 40%);">- * after cache-as-ram is torn down. It also contains the information</span><br><span style="color: hsl(0, 100%, 40%);">- * for setting up MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x30)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x31)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x32)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x33)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x36)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x38)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear all of the variable MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- clr %eax</span><br><span style="color: hsl(0, 100%, 40%);">- clr %edx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- testl %ebx, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jz 1f</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr /* Write MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr /* Write MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- dec %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jmp 1b</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Get number of MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-2:</span><br><span style="color: hsl(0, 100%, 40%);">- testl %ebx, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jz 2f</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dec %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jmp 2b</span><br><span style="color: hsl(0, 100%, 40%);">-2:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x39)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* And enable cache again after setting MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3a)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_DEF_TYPE_EN, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3b)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Invalidate the cache again. */</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3c)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-__main:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PREPARE_RAMSTAGE)</span><br><span style="color: hsl(0, 100%, 40%);">- cld /* Clear direction flag. */</span><br><span style="color: hsl(0, 100%, 40%);">- call romstage_after_car</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-.Lhlt:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_DEAD_CODE)</span><br><span style="color: hsl(0, 100%, 40%);">- hlt</span><br><span style="color: hsl(0, 100%, 40%);">- jmp .Lhlt</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-mtrr_table:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Fixed MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x250, 0x258, 0x259</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x268, 0x269, 0x26A</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x26B, 0x26C, 0x26D</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x26E, 0x26F</span><br><span style="color: hsl(0, 100%, 40%);">- /* Variable MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x200, 0x201, 0x202, 0x203</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x204, 0x205, 0x206, 0x207</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x208, 0x209, 0x20A, 0x20B</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x20C, 0x20D, 0x20E, 0x20F</span><br><span style="color: hsl(0, 100%, 40%);">-mtrr_table_end:</span><br><span>diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc</span><br><span>index f33b409..05514a1 100644</span><br><span>--- a/src/cpu/intel/socket_BGA956/Makefile.inc</span><br><span>+++ b/src/cpu/intel/socket_BGA956/Makefile.inc</span><br><span>@@ -8,11 +8,7 @@</span><br><span> subdirs-y += ../hyperthreading</span><br><span> subdirs-y += ../speedstep</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ifneq ($(CONFIG_POSTCAR_STAGE),y)</span><br><span style="color: hsl(0, 100%, 40%);">-cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span style="color: hsl(0, 100%, 40%);">-else</span><br><span> cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S</span><br><span> postcar-y += ../car/p4-netburst/exit_car.S</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span> </span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc</span><br><span>index ef89ac6..78d7c0e 100644</span><br><span>--- a/src/cpu/intel/socket_mPGA478MN/Makefile.inc</span><br><span>+++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc</span><br><span>@@ -9,11 +9,7 @@</span><br><span> subdirs-y += ../hyperthreading</span><br><span> subdirs-y += ../speedstep</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ifneq ($(CONFIG_POSTCAR_STAGE),y)</span><br><span style="color: hsl(0, 100%, 40%);">-cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span style="color: hsl(0, 100%, 40%);">-else</span><br><span> cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S</span><br><span> postcar-y += ../car/p4-netburst/exit_car.S</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span> </span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig</span><br><span>index 85902d3..193ec70 100644</span><br><span>--- a/src/northbridge/intel/gm45/Kconfig</span><br><span>+++ b/src/northbridge/intel/gm45/Kconfig</span><br><span>@@ -29,6 +29,8 @@</span><br><span> select RELOCATABLE_RAMSTAGE</span><br><span> select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span> select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_CONSOLE</span><br><span> </span><br><span> config CBFS_SIZE</span><br><span> hex</span><br><span>diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc</span><br><span>index fdf0012..c12bbf1 100644</span><br><span>--- a/src/northbridge/intel/gm45/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/gm45/Makefile.inc</span><br><span>@@ -36,4 +36,6 @@</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ram_calc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>index 9b70523..c986ffe 100644</span><br><span>--- a/src/northbridge/intel/gm45/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>@@ -118,9 +118,10 @@</span><br><span> </span><br><span> #define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* setup_stack_and_mtrrs() determines the stack to use after</span><br><span style="color: hsl(0, 100%, 40%);">- * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span style="color: hsl(0, 100%, 40%);">-void *setup_stack_and_mtrrs(void)</span><br><span style="color: hsl(120, 100%, 40%);">+/* platform_enter_postcar() determines the stack to use after</span><br><span style="color: hsl(120, 100%, 40%);">+ * cache-as-ram is torn down as well as the MTRR settings to use,</span><br><span style="color: hsl(120, 100%, 40%);">+ * and continues execution in postcar stage. */</span><br><span style="color: hsl(120, 100%, 40%);">+void platform_enter_postcar(void)</span><br><span> {</span><br><span> struct postcar_frame pcf;</span><br><span> uintptr_t top_of_ram;</span><br><span>@@ -144,8 +145,7 @@</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the number of MTRRs to setup. Return the stack location</span><br><span style="color: hsl(0, 100%, 40%);">- * pointing to the number of MTRRs.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- return postcar_commit_mtrrs(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+ run_postcar_phase(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We do not return here. */</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26788">change 26788</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26788"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I02165cf63710bedcafe9287cbe8a1d1fe41ebae2 </div>
<div style="display:none"> Gerrit-Change-Number: 26788 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>