<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26777">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/kahlee: Remove Kahlee variant<br><br>This code is no longer needed. Removing Kahlee options allows some<br>Kconfig options to be optimized.<br><br>BUG=b:77693343<br>TEST=Build Grunt, verify that nothing's changed.<br><br>Change-Id: I4eeeee7f35381bba8760c8a530251c475d0ee29b<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/mainboard/google/kahlee/BiosCallOuts.c<br>M src/mainboard/google/kahlee/Kconfig<br>M src/mainboard/google/kahlee/Kconfig.name<br>M src/mainboard/google/kahlee/mainboard.c<br>D src/mainboard/google/kahlee/variants/kahlee/Makefile.inc<br>D src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c<br>D src/mainboard/google/kahlee/variants/kahlee/chromeos.fmd<br>D src/mainboard/google/kahlee/variants/kahlee/devicetree.cb<br>D src/mainboard/google/kahlee/variants/kahlee/gpio.c<br>D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/audio.asl<br>D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/gpe.asl<br>D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/mainboard.asl<br>D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/routing.asl<br>D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/sleep.asl<br>D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/thermal.asl<br>D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/touchpad.asl<br>D src/mainboard/google/kahlee/variants/kahlee/include/variant/ec.h<br>D src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h<br>D src/mainboard/google/kahlee/variants/kahlee/include/variant/thermal.h<br>D src/mainboard/google/kahlee/variants/kahlee/memory.c<br>20 files changed, 9 insertions(+), 778 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/26777/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c</span><br><span>index 2ed1843..7f7e575 100644</span><br><span>--- a/src/mainboard/google/kahlee/BiosCallOuts.c</span><br><span>+++ b/src/mainboard/google/kahlee/BiosCallOuts.c</span><br><span>@@ -15,13 +15,7 @@</span><br><span> </span><br><span> #include <amdblocks/agesawrapper.h></span><br><span> #include <amdblocks/BiosCallOuts.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/southbridge.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span> </span><br><span> void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* SDHCI/MMC configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE))</span><br><span style="color: hsl(0, 100%, 40%);">- FchParams_env->Sd.SdSlotType = 1; // EMMC</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig</span><br><span>index b44e3bd..03d5265 100644</span><br><span>--- a/src/mainboard/google/kahlee/Kconfig</span><br><span>+++ b/src/mainboard/google/kahlee/Kconfig</span><br><span>@@ -18,8 +18,7 @@</span><br><span> select SOC_AMD_STONEYRIDGE_FT4</span><br><span> select ALWAYS_LOAD_OPROM</span><br><span> select ALWAYS_RUN_OPROM</span><br><span style="color: hsl(0, 100%, 40%);">- select BOARD_ROMSIZE_KB_8192 if BOARD_GOOGLE_KAHLEE</span><br><span style="color: hsl(0, 100%, 40%);">- select BOARD_ROMSIZE_KB_16384 if !BOARD_GOOGLE_KAHLEE</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_16384</span><br><span> select DRIVERS_I2C_GENERIC</span><br><span> select DRIVERS_PS2_KEYBOARD</span><br><span> select EC_GOOGLE_CHROMEEC</span><br><span>@@ -30,13 +29,18 @@</span><br><span> select GFXUMA</span><br><span> select GOOGLE_SMBIOS_MAINBOARD_VERSION</span><br><span> select MAINBOARD_HAS_CHROMEOS</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_LPC_TPM if BOARD_GOOGLE_KAHLEE</span><br><span> select SERIRQ_CONTINUOUS_MODE</span><br><span> select STONEYRIDGE_UART</span><br><span> select SOC_AMD_PSP_SELECTABLE_SMU_FW</span><br><span> select SOC_AMD_SMU_FANLESS</span><br><span> select HAVE_ACPI_RESUME</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_GENERIC_BH720 if !BOARD_GOOGLE_KAHLEE</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_GENERIC_BH720</span><br><span style="color: hsl(120, 100%, 40%);">+ select I2C_TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_I2C_TPM_CR50</span><br><span style="color: hsl(120, 100%, 40%);">+ select TPM2</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_GENERIC_ADAU7002</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_GENERIC_MAX98357A</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_DA7219</span><br><span> </span><br><span> if BOARD_GOOGLE_BASEBOARD_KAHLEE</span><br><span> </span><br><span>@@ -48,13 +52,11 @@</span><br><span> string</span><br><span> default "careena" if BOARD_GOOGLE_CAREENA</span><br><span> default "grunt" if BOARD_GOOGLE_GRUNT</span><br><span style="color: hsl(0, 100%, 40%);">- default "kahlee" if BOARD_GOOGLE_KAHLEE</span><br><span> </span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span> default "Careena" if BOARD_GOOGLE_CAREENA</span><br><span> default "Grunt" if BOARD_GOOGLE_GRUNT</span><br><span style="color: hsl(0, 100%, 40%);">- default "Kahlee" if BOARD_GOOGLE_KAHLEE</span><br><span> </span><br><span> config DEVICETREE</span><br><span> string</span><br><span>@@ -66,7 +68,6 @@</span><br><span> </span><br><span> config FMDFILE</span><br><span> string</span><br><span style="color: hsl(0, 100%, 40%);">- default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/$(CONFIG_VARIANT_DIR)/chromeos.fmd" if CHROMEOS && BOARD_GOOGLE_KAHLEE</span><br><span> default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/baseboard/chromeos.fmd" if CHROMEOS</span><br><span> default ""</span><br><span> help</span><br><span>@@ -102,35 +103,17 @@</span><br><span> depends on CHROMEOS</span><br><span> default "CAREENA TEST 8777" if BOARD_GOOGLE_CAREENA</span><br><span> default "GRUNT TEST 8296" if BOARD_GOOGLE_GRUNT</span><br><span style="color: hsl(0, 100%, 40%);">- default "KAHLEE TEST 6421" if BOARD_GOOGLE_KAHLEE</span><br><span> </span><br><span> config AMD_FWM_POSITION_INDEX</span><br><span> int</span><br><span> default 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-# Select this option to enable use of cr50 I2C TPM on kahlee</span><br><span style="color: hsl(0, 100%, 40%);">-config KAHLEE_USE_I2C_TPM</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- default y if !BOARD_GOOGLE_KAHLEE</span><br><span style="color: hsl(0, 100%, 40%);">- select I2C_TPM</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_I2C_TPM_CR50</span><br><span style="color: hsl(0, 100%, 40%);">- select TPM2</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config DRIVER_TPM_I2C_BUS</span><br><span> hex</span><br><span style="color: hsl(0, 100%, 40%);">- depends on KAHLEE_USE_I2C_TPM</span><br><span> default 0x01</span><br><span> </span><br><span> config DRIVER_TPM_I2C_ADDR</span><br><span> hex</span><br><span style="color: hsl(0, 100%, 40%);">- depends on KAHLEE_USE_I2C_TPM</span><br><span> default 0x50</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config GRUNT_AUDIO</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- default y if !BOARD_GOOGLE_KAHLEE</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_GENERIC_ADAU7002</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_GENERIC_MAX98357A</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_I2C_DA7219</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> endif # BOARD_GOOGLE_BASEBOARD_KAHLEE</span><br><span>diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name</span><br><span>index 98f9be1..4f58a01 100644</span><br><span>--- a/src/mainboard/google/kahlee/Kconfig.name</span><br><span>+++ b/src/mainboard/google/kahlee/Kconfig.name</span><br><span>@@ -6,6 +6,3 @@</span><br><span> config BOARD_GOOGLE_GRUNT</span><br><span> bool "-> Grunt"</span><br><span> select BOARD_GOOGLE_BASEBOARD_KAHLEE</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_GOOGLE_KAHLEE</span><br><span style="color: hsl(0, 100%, 40%);">- bool "-> Kahlee"</span><br><span style="color: hsl(0, 100%, 40%);">- select BOARD_GOOGLE_BASEBOARD_KAHLEE</span><br><span>diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c</span><br><span>index e090401..c2c9be3 100644</span><br><span>--- a/src/mainboard/google/kahlee/mainboard.c</span><br><span>+++ b/src/mainboard/google/kahlee/mainboard.c</span><br><span>@@ -44,46 +44,6 @@</span><br><span> * MP Tables. TODO: Make ACPI use these values too.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-// TODO: Move these to board variant specific file</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE)</span><br><span style="color: hsl(0, 100%, 40%);">-const u8 mainboard_picr_data[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x03,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x40] = 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const u8 mainboard_intr_data[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,</span><br><span style="color: hsl(0, 100%, 40%);">- [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span> const u8 mainboard_picr_data[] = {</span><br><span> [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x1F, 0x1F, 0x1F,</span><br><span> [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,</span><br><span>@@ -121,7 +81,6 @@</span><br><span> [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,</span><br><span> [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span> };</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> </span><br><span> /*</span><br><span> * This table defines the index into the picr/intr_data tables for each</span><br><span>@@ -184,9 +143,7 @@</span><br><span> i2c_soc_init();</span><br><span> </span><br><span> /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE))</span><br><span style="color: hsl(0, 100%, 40%);">- pm_write8(PM_PCIB_CFG,</span><br><span style="color: hsl(0, 100%, 40%);">- pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);</span><br><span> }</span><br><span> </span><br><span> /*************************************************</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index ab91501..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,23 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-#</span><br><span style="color: hsl(0, 100%, 40%);">-# This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-#</span><br><span style="color: hsl(0, 100%, 40%);">-# Copyright (C) 2017 Google, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">-#</span><br><span style="color: hsl(0, 100%, 40%);">-# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">-# the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">-#</span><br><span style="color: hsl(0, 100%, 40%);">-# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-# GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-#</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += OemCustomize.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += OemCustomize.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += memory.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += gpio.c</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c</span><br><span>deleted file mode 100644</span><br><span>index 568ed31..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,126 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <amdblocks/agesawrapper.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <variant/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const PCIe_PORT_DESCRIPTOR PortList[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,</span><br><span style="color: hsl(0, 100%, 40%);">- 2, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported,</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, 0, 0)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,</span><br><span style="color: hsl(0, 100%, 40%);">- 2, 2,</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported,</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, PCIE_0_RST, 0)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) for Card Reader */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,</span><br><span style="color: hsl(0, 100%, 40%);">- 2, 3,</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported,</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, PCIE_1_RST, 0)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for NC */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,</span><br><span style="color: hsl(0, 100%, 40%);">- 2, 4,</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported,</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, PCIE_2_RST, 0)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,</span><br><span style="color: hsl(0, 100%, 40%);">- 2, 5,</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported,</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, PCIE_3_RST, 0)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const PCIe_DDI_DESCRIPTOR DdiList[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* DDI0 - eDP */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- /* DDI1 - DP */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- /* DDI2 - DP */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {</span><br><span style="color: hsl(0, 100%, 40%);">- .Flags = DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(0, 100%, 40%);">- .SocketId = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- .PciePortList = (void *)PortList,</span><br><span style="color: hsl(0, 100%, 40%);">- .DdiLinkList = (void *)DdiList</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*---------------------------------------------------------------------------*/</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * OemCustomizeInitEarly</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Description:</span><br><span style="color: hsl(0, 100%, 40%);">- * This is the stub function will call the host environment through the</span><br><span style="color: hsl(0, 100%, 40%);">- * binary block interface (call-out port) to provide a user hook opportunity.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Parameters:</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in] **PeiServices</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in] *InitEarly</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @retval VOID</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- **/</span><br><span style="color: hsl(0, 100%, 40%);">-/*---------------------------------------------------------------------------*/</span><br><span style="color: hsl(0, 100%, 40%);">-VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;</span><br><span style="color: hsl(0, 100%, 40%);">- InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;</span><br><span style="color: hsl(0, 100%, 40%);">- InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/chromeos.fmd b/src/mainboard/google/kahlee/variants/kahlee/chromeos.fmd</span><br><span>deleted file mode 100644</span><br><span>index 4a4e3ca..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/chromeos.fmd</span><br><span>+++ /dev/null</span><br><span>@@ -1,40 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-FLASH@0xFF800000 0x800000 {</span><br><span style="color: hsl(0, 100%, 40%);">- SI_BIOS@0x0 0x800000 {</span><br><span style="color: hsl(0, 100%, 40%);">- RW_SECTION_A@0x0 0x21E000 {</span><br><span style="color: hsl(0, 100%, 40%);">- VBLOCK_A@0x0 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">- FW_MAIN_A(CBFS)@0x10000 0x20DFC0</span><br><span style="color: hsl(0, 100%, 40%);">- RW_FWID_A@0x21DFC0 0x40</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_SECTION_B@0x21E000 0x21E000 {</span><br><span style="color: hsl(0, 100%, 40%);">- VBLOCK_B@0x0 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">- FW_MAIN_B(CBFS)@0x10000 0x20DFC0</span><br><span style="color: hsl(0, 100%, 40%);">- RW_FWID_B@0x21DFC0 0x40</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- UNIFIED_MRC_CACHE@0x43C000 0x21000 {</span><br><span style="color: hsl(0, 100%, 40%);">- RECOVERY_MRC_CACHE@0x0 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_MRC_CACHE@0x10000 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_VAR_MRC_CACHE@0x20000 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_ELOG@0x45D000 0x4000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- RW_SHARED@0x461000 0x4000 {</span><br><span style="color: hsl(0, 100%, 40%);">- SHARED_DATA@0x0 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">- VBLOCK_DEV@0x2000 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_VPD@0x465000 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_LEGACY@0x467000 0x100000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_NVRAM@0x567000 0x5000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_UNUSED@0x56C000 0x3000</span><br><span style="color: hsl(0, 100%, 40%);">- WP_RO@0x56F000 0x291000 {</span><br><span style="color: hsl(0, 100%, 40%);">- RO_VPD@0x0 0x4000</span><br><span style="color: hsl(0, 100%, 40%);">- RO_UNUSED@0x4000 0xc000</span><br><span style="color: hsl(0, 100%, 40%);">- RO_SECTION@0x10000 0x281000 {</span><br><span style="color: hsl(0, 100%, 40%);">- FMAP@0x0 0x800</span><br><span style="color: hsl(0, 100%, 40%);">- RO_FRID@0x800 0x40</span><br><span style="color: hsl(0, 100%, 40%);">- RO_FRID_PAD@0x840 0x7c0</span><br><span style="color: hsl(0, 100%, 40%);">- GBB@0x1000 0x70000</span><br><span style="color: hsl(0, 100%, 40%);">- COREBOOT(CBFS)@0x71000 0x210000</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb</span><br><span>deleted file mode 100644</span><br><span>index 22456b0..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb</span><br><span>+++ /dev/null</span><br><span>@@ -1,67 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-#</span><br><span style="color: hsl(0, 100%, 40%);">-# This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-#</span><br><span style="color: hsl(0, 100%, 40%);">-# Copyright (C) 2015-2017 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">-#</span><br><span style="color: hsl(0, 100%, 40%);">-# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">-# the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">-#</span><br><span style="color: hsl(0, 100%, 40%);">-# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-# GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-#</span><br><span style="color: hsl(0, 100%, 40%);">-chip soc/amd/stoneyridge</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- register "spd_addr_lookup" = "</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0</span><br><span style="color: hsl(0, 100%, 40%);">- }"</span><br><span style="color: hsl(0, 100%, 40%);">- register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"</span><br><span style="color: hsl(0, 100%, 40%);">- register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"</span><br><span style="color: hsl(0, 100%, 40%);">- register "uma_size" = "32 * MiB"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- device cpu_cluster 0 on</span><br><span style="color: hsl(0, 100%, 40%);">- device lapic 10 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device domain 0 on</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x1022 0x1410 inherit</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 0.0 on end # Root Complex</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1.1 on end # Internal Multimedia</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 2.0 on end # PCIe Host Bridge</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 2.1 on end # x4 PCIe slot</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 2.2 on end # M.2 slot</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 2.3 on end # M.2 slot</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 2.4 on end # x1 PCIe slot</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 2.5 on end # Cardreader</span><br><span style="color: hsl(0, 100%, 40%);">- # devices on the NB/SB Link, but on the same pci bus</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 8.0 on end # PSP</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 9.0 on end # PCIe Host Bridge</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 9.2 on end # HDA</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 10.0 on end # xHCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 11.0 on end # SATA</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 12.0 on end # EHCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on # SM</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/generic/generic # dimm 0-0-0</span><br><span style="color: hsl(0, 100%, 40%);">- device i2c 50 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end # SM</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.3 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip ec/google/chromeec</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c09.0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end # LPC 0x790e</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.7 on end # SD</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 18.0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 18.1 on end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 18.2 on end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 18.3 on end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 18.4 on end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 18.5 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end #domain</span><br><span style="color: hsl(0, 100%, 40%);">-end #chip soc/amd/stoneyridge</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c</span><br><span>deleted file mode 100644</span><br><span>index 3072350..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,159 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/smi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/southbridge.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <variant/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * As a rule of thumb, GPIO pins used by coreboot should be initialized at</span><br><span style="color: hsl(0, 100%, 40%);">- * bootblock while GPIO pins used only by the OS should be initialized at</span><br><span style="color: hsl(0, 100%, 40%);">- * ramstage.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct soc_amd_gpio gpio_set_stage_reset[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* AGPIO2, to become event generator */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_SCI(GPIO_2, PULL_UP, EDGE_LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* SER_TX */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_8, SerPortTX_OUT, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* SER RX */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_9, SerPortRX_OUT, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* EC_IN_RW */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_15, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* APU_I2C_3_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* APU_I2C_3_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* AGPIO22 EC_SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* SPI_TPM_CS_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_76, SPI_TPM_CS_L, PULL_DOWN),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* BD_ID1 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_135, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_136 - UART_FCH_RX_DEBUG_RX */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_138 - UART_FCH_TX_DEBUG_RX */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TPM_SERIRQ# */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_139, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* BD_ID2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_140, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* APU_SPI_WP */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_142, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* BD_ID3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_144, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct soc_amd_gpio gpio_set_stage_ram[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* AGPIO 12 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_12, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TS_EN_SOC (TouchScreen enable GPIO) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_13, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* CAM_PWRON (Camera enable GPIO) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_14, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* APU_BT_ON# */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_24, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* DEVSLP1_SSD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_67, DEVSLP0, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* DEVSLP1_EMMC */</span><br><span style="color: hsl(0, 100%, 40%);">- /* No Connect for now.</span><br><span style="color: hsl(0, 100%, 40%);">- * {GPIO_70, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT},</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* CAM_LED# */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_84, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TS_RST# (TouchScreen Reset) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_85, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* WLAN_RST#_AUX */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_119, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_gpio *variant_early_gpio_table(size_t *size)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- *size = ARRAY_SIZE(gpio_set_stage_reset);</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_set_stage_reset;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_gpio *variant_gpio_table(size_t *size)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- *size = ARRAY_SIZE(gpio_set_stage_ram);</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_set_stage_ram;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * GPE setup table must match ACPI GPE ASL</span><br><span style="color: hsl(0, 100%, 40%);">- * { gevent, gpe, direction, level }</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct sci_source gpe_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* EHCI USB_PME -> GPE24 */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- .scimap = 24,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpe = 24,</span><br><span style="color: hsl(0, 100%, 40%);">- .direction = SMI_SCI_LVL_HIGH,</span><br><span style="color: hsl(0, 100%, 40%);">- .level = SMI_SCI_LVL,</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* XHCIC0 -> GPE31 */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- .scimap = 56,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpe = 31,</span><br><span style="color: hsl(0, 100%, 40%);">- .direction = SMI_SCI_LVL_HIGH,</span><br><span style="color: hsl(0, 100%, 40%);">- .level = SMI_SCI_LVL,</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct sci_source *get_gpe_table(size_t *num)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- *num = ARRAY_SIZE(gpe_table);</span><br><span style="color: hsl(0, 100%, 40%);">- return gpe_table;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int variant_get_xhci_oc_map(uint16_t *map)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- *map = USB_OC2 << OC_PORT0_SHIFT; /* USB-A Port0/4 = OC2 */</span><br><span style="color: hsl(0, 100%, 40%);">- *map |= USB_OC0 << OC_PORT1_SHIFT; /* USB-C Port1/5 = OC0 */</span><br><span style="color: hsl(0, 100%, 40%);">- *map |= USB_OC1 << OC_PORT2_SHIFT; /* USB-C Port2/6 = OC1 */</span><br><span style="color: hsl(0, 100%, 40%);">- *map |= USB_OC_DISABLE << OC_PORT3_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int variant_get_ehci_oc_map(uint16_t *map)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- *map = USB_OC_DISABLE_ALL;</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/audio.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/audio.asl</span><br><span>deleted file mode 100644</span><br><span>index 031eafc..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/audio.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,55 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2018 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Realtek Audio Codec */</span><br><span style="color: hsl(0, 100%, 40%);">-Device (RTEK) /* Audio Codec driver I2CS*/</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_ADR, 0)</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_HID, "10EC5650")</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_CID, "10EC5650")</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_DDN, "RTEK Codec Controller ")</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_UID, 1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Device (I2S) /* I2S machine driver for RT5650 */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_ADR, 1)</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_HID, "AMDI1002")</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_CID, "AMDI1002")</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Method (_CRS, 0x0, Serialized)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- Name (SBUF, ResourceTemplate ()</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- I2CSerialBus(</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1A, /* SlaveAddress: bus address */</span><br><span style="color: hsl(0, 100%, 40%);">- ControllerInitiated, /* SlaveMode: default to ControllerInitiated */</span><br><span style="color: hsl(0, 100%, 40%);">- 400000, /* ConnectionSpeed: in Hz */</span><br><span style="color: hsl(0, 100%, 40%);">- AddressingMode7Bit, /* Addressing Mode: default to 7 bit */</span><br><span style="color: hsl(0, 100%, 40%);">- "\\_SB.I2CA", /* ResourceSource: I2C bus controller name */</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Jack Detect AGPIO90 */</span><br><span style="color: hsl(0, 100%, 40%);">- GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,</span><br><span style="color: hsl(0, 100%, 40%);">- "\\_SB.GPIO") { 90 }</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">- Return (SBUF)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Method (_STA)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (0xF)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/gpe.asl</span><br><span>deleted file mode 100644</span><br><span>index 0a08774..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/gpe.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,16 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2018 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/acpi/gpe.asl></span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/mainboard.asl</span><br><span>deleted file mode 100644</span><br><span>index 159f935..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/mainboard.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,18 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2018 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/acpi/mainboard.asl></span><br><span style="color: hsl(0, 100%, 40%);">-#include <variant/acpi/audio.asl></span><br><span style="color: hsl(0, 100%, 40%);">-#include <variant/acpi/touchpad.asl></span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/routing.asl</span><br><span>deleted file mode 100644</span><br><span>index 233494f..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/routing.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,16 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2018 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/acpi/routing.asl></span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/sleep.asl</span><br><span>deleted file mode 100644</span><br><span>index c5a1557..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/sleep.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,16 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2018 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/acpi/sleep.asl></span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/thermal.asl</span><br><span>deleted file mode 100644</span><br><span>index 77137bb..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/thermal.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,16 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2018 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/acpi/thermal.asl></span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/touchpad.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/touchpad.asl</span><br><span>deleted file mode 100644</span><br><span>index 2babaf2..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/touchpad.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,38 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2018 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Device (ETPA)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_HID, "ELAN0000")</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_DDN, "Elan Touchpad")</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_UID, 1)</span><br><span style="color: hsl(0, 100%, 40%);">- Name (ISTP, 1) /* Touchpad */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_CRS, ResourceTemplate()</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- I2cSerialBus (</span><br><span style="color: hsl(0, 100%, 40%);">- 0x15, /* SlaveAddress */</span><br><span style="color: hsl(0, 100%, 40%);">- ControllerInitiated, /* SlaveMode */</span><br><span style="color: hsl(0, 100%, 40%);">- 400000, /* ConnectionSpeed */</span><br><span style="color: hsl(0, 100%, 40%);">- AddressingMode7Bit, /* AddressingMode */</span><br><span style="color: hsl(0, 100%, 40%);">- "\\_SB.I2CD", /* ResourceSource */</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">- GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,,</span><br><span style="color: hsl(0, 100%, 40%);">- "\\_SB.GPIO") { 0x5 }</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Allow device to power off in S0 */</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_S0W, 3)</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/ec.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/ec.h</span><br><span>deleted file mode 100644</span><br><span>index 294a48d..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/ec.h</span><br><span>+++ /dev/null</span><br><span>@@ -1 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/ec.h></span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h</span><br><span>deleted file mode 100644</span><br><span>index 361e1eb..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,51 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __VARIANT_GPIO_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __VARIANT_GPIO_H__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Kahlee doesn't use MEM_CONFIG GPIOs, but they are required to build</span><br><span style="color: hsl(0, 100%, 40%);">- * the baseboard weak memory_sku function.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_CONFIG0 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_CONFIG1 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_CONFIG2 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_CONFIG3 0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* CDX03 doesn't have a CR50 interrupt pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define H1_PCH_INT 0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI Write protect */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CROS_WP_GPIO GPIO_142</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_EC_IN_RW GPIO_15</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* PCIe reset pins */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCIE_0_RST GPIO_119</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCIE_1_RST 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCIE_2_RST 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCIE_3_RST 0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* _ACPI__ */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* These define the GPE, not the GPIO. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_SCI_GPI 3 /* AGPIO 22 -> GPE 3 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_SMI_GPI 10 /* AGPIO 6 -> GPE 10 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_WAKE_GPI 8 /* AGPIO 2 -> GPE 8 */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* __VARIANT_GPIO_H__ */</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/thermal.h</span><br><span>deleted file mode 100644</span><br><span>index 2c983bb..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/thermal.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,38 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef THERMAL_H</span><br><span style="color: hsl(0, 100%, 40%);">-#define THERMAL_H</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Stoney Ridge Thermal Requirements 12 (6W)</span><br><span style="color: hsl(0, 100%, 40%);">- * TDP (W) 6</span><br><span style="color: hsl(0, 100%, 40%);">- * T die,max (°C) 95</span><br><span style="color: hsl(0, 100%, 40%);">- * T ctl,max 85</span><br><span style="color: hsl(0, 100%, 40%);">- * T die,lmt (default) 90</span><br><span style="color: hsl(0, 100%, 40%);">- * T ctl,lmt (default) 80</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Control TDP Settings */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CTL_TDP_SENSOR_ID 0 /* EC TIN0 */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Temperature which OS will shutdown at */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CRITICAL_TEMPERATURE 94</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Temperature which OS will throttle CPU */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PASSIVE_TEMPERATURE 85</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/memory.c b/src/mainboard/google/kahlee/variants/kahlee/memory.c</span><br><span>deleted file mode 100644</span><br><span>index 1c7c8a1..0000000</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/memory.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,20 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Return error so the default I2C SPD read is used */</span><br><span style="color: hsl(0, 100%, 40%);">- return -1;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26777">change 26777</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26777"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4eeeee7f35381bba8760c8a530251c475d0ee29b </div>
<div style="display:none"> Gerrit-Change-Number: 26777 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>